···1054{1055 struct pci_dev *pci_dev = efx->pci_dev;1056 dma_addr_t dma_mask = efx->type->max_dma_mask;01057 int rc;10581059 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");···1105 rc = -EIO;1106 goto fail3;1107 }1108- efx->membase = ioremap_wc(efx->membase_phys,1109- efx->type->mem_map_size);00000000000001110 if (!efx->membase) {1111 netif_err(efx, probe, efx->net_dev,1112 "could not map memory BAR at %llx+%x\n",
···1054{1055 struct pci_dev *pci_dev = efx->pci_dev;1056 dma_addr_t dma_mask = efx->type->max_dma_mask;1057+ bool use_wc;1058 int rc;10591060 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");···1104 rc = -EIO;1105 goto fail3;1106 }1107+1108+ /* bug22643: If SR-IOV is enabled then tx push over a write combined1109+ * mapping is unsafe. We need to disable write combining in this case.1110+ * MSI is unsupported when SR-IOV is enabled, and the firmware will1111+ * have removed the MSI capability. So write combining is safe if1112+ * there is an MSI capability.1113+ */1114+ use_wc = (!EFX_WORKAROUND_22643(efx) ||1115+ pci_find_capability(pci_dev, PCI_CAP_ID_MSI));1116+ if (use_wc)1117+ efx->membase = ioremap_wc(efx->membase_phys,1118+ efx->type->mem_map_size);1119+ else1120+ efx->membase = ioremap_nocache(efx->membase_phys,1121+ efx->type->mem_map_size);1122 if (!efx->membase) {1123 netif_err(efx, probe, efx->net_dev,1124 "could not map memory BAR at %llx+%x\n",