···5454#include <linux/pm.h>5555#include <linux/timex.h>5656#include <linux/vmalloc.h>5757+#include <linux/mv643xx.h>57585859#include <asm/time.h>5960#include <asm/bootinfo.h>···6564#include <asm/processor.h>6665#include <asm/ptrace.h>6766#include <asm/reboot.h>6767+#include <asm/marvell.h>6868#include <linux/bootmem.h>6969#include <linux/blkdev.h>7070-#include <asm/mv64340.h>7170#include "ocelot_c_fpga.h"72717372unsigned long marvell_base;···253252 /* shut down ethernet ports, just to be sure our memory doesn't get254253 * corrupted by random ethernet traffic.255254 */256256- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);257257- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);258258- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);259259- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);255255+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);256256+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);257257+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);258258+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);260259 do {}261261- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);260260+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);262261 do {}263263- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);262262+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);264263 do {}265265- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);264264+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);266265 do {}267267- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);268268- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),269269- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);270270- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),271271- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);266266+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);267267+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),268268+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);269269+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),270270+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);272271273272 /* Turn off the Bit-Error LED */274273 OCELOT_FPGA_WRITE(0x80, CLR);
+4-2
arch/mips/pci/pci-ocelot-c.c
···33 * License. See the file "COPYING" in the main directory of this archive44 * for more details.55 *66- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)66+ * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)77 */8899#include <linux/types.h>1010#include <linux/pci.h>1111-#include <asm/mv64340.h>1111+#include <linux/mv643xx.h>12121313#include <linux/init.h>1414+1515+#include <asm/marvell.h>14161517/*1618 * We assume the address ranges have already been setup appropriately by