···54#include <linux/pm.h>55#include <linux/timex.h>56#include <linux/vmalloc.h>05758#include <asm/time.h>59#include <asm/bootinfo.h>···65#include <asm/processor.h>66#include <asm/ptrace.h>67#include <asm/reboot.h>068#include <linux/bootmem.h>69#include <linux/blkdev.h>70-#include <asm/mv64340.h>71#include "ocelot_c_fpga.h"7273unsigned long marvell_base;···253 /* shut down ethernet ports, just to be sure our memory doesn't get254 * corrupted by random ethernet traffic.255 */256- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);257- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);258- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);259- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);260 do {}261- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);262 do {}263- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);264 do {}265- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);266 do {}267- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);268- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),269- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);270- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),271- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);272273 /* Turn off the Bit-Error LED */274 OCELOT_FPGA_WRITE(0x80, CLR);
···54#include <linux/pm.h>55#include <linux/timex.h>56#include <linux/vmalloc.h>57+#include <linux/mv643xx.h>5859#include <asm/time.h>60#include <asm/bootinfo.h>···64#include <asm/processor.h>65#include <asm/ptrace.h>66#include <asm/reboot.h>67+#include <asm/marvell.h>68#include <linux/bootmem.h>69#include <linux/blkdev.h>070#include "ocelot_c_fpga.h"7172unsigned long marvell_base;···252 /* shut down ethernet ports, just to be sure our memory doesn't get253 * corrupted by random ethernet traffic.254 */255+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);256+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);257+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);258+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);259 do {}260+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);261 do {}262+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);263 do {}264+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);265 do {}266+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);267+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),268+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);269+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),270+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);271272 /* Turn off the Bit-Error LED */273 OCELOT_FPGA_WRITE(0x80, CLR);
+4-2
arch/mips/pci/pci-ocelot-c.c
···3 * License. See the file "COPYING" in the main directory of this archive4 * for more details.5 *6- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)7 */89#include <linux/types.h>10#include <linux/pci.h>11-#include <asm/mv64340.h>1213#include <linux/init.h>001415/*16 * We assume the address ranges have already been setup appropriately by
···3 * License. See the file "COPYING" in the main directory of this archive4 * for more details.5 *6+ * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)7 */89#include <linux/types.h>10#include <linux/pci.h>11+#include <linux/mv643xx.h>1213#include <linux/init.h>14+15+#include <asm/marvell.h>1617/*18 * We assume the address ranges have already been setup appropriately by