···9797}98989999static int100100-nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl,101101- u8 id, u32 khz)102102-{103103- struct drm_nouveau_private *dev_priv = dev->dev_private;104104- struct nouveau_pm_engine *pm = &dev_priv->engine.pm;105105- void *pre_state;106106-107107- if (khz == 0)108108- return 0;109109-110110- pre_state = pm->clock_pre(dev, perflvl, id, khz);111111- if (IS_ERR(pre_state))112112- return PTR_ERR(pre_state);113113-114114- if (pre_state)115115- pm->clock_set(dev, pre_state);116116- return 0;117117-}118118-119119-static int120100nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)121101{122102 struct drm_nouveau_private *dev_priv = dev->dev_private;123103 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;104104+ void *state;124105 int ret;125106126107 if (perflvl == pm->cur)···125144 }126145 }127146128128- if (pm->clocks_pre) {129129- void *state = pm->clocks_pre(dev, perflvl);130130- if (IS_ERR(state))131131- return PTR_ERR(state);132132- pm->clocks_set(dev, state);133133- } else134134- if (pm->clock_set) {135135- nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core);136136- nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader);137137- nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);138138- nouveau_pm_clock_set(dev, perflvl, PLL_VDEC, perflvl->vdec);139139- }147147+ state = pm->clocks_pre(dev, perflvl);148148+ if (IS_ERR(state))149149+ return PTR_ERR(state);150150+ pm->clocks_set(dev, state);140151141152 pm->cur = perflvl;142153 return 0;···175202176203 memset(perflvl, 0, sizeof(*perflvl));177204178178- if (pm->clocks_get) {179179- ret = pm->clocks_get(dev, perflvl);180180- if (ret)181181- return ret;182182- } else183183- if (pm->clock_get) {184184- ret = pm->clock_get(dev, PLL_CORE);185185- if (ret > 0)186186- perflvl->core = ret;187187-188188- ret = pm->clock_get(dev, PLL_MEMORY);189189- if (ret > 0)190190- perflvl->memory = ret;191191-192192- ret = pm->clock_get(dev, PLL_SHADER);193193- if (ret > 0)194194- perflvl->shader = ret;195195-196196- ret = pm->clock_get(dev, PLL_VDEC);197197- if (ret > 0)198198- perflvl->vdec = ret;199199- }205205+ ret = pm->clocks_get(dev, perflvl);206206+ if (ret)207207+ return ret;200208201209 if (pm->voltage.supported && pm->voltage_get) {202210 ret = pm->voltage_get(dev);
+2-1
drivers/gpu/drm/nouveau/nv04_timer.c
···22#include "drm.h"33#include "nouveau_drv.h"44#include "nouveau_drm.h"55+#include "nouveau_hw.h"5667int78nv04_timer_init(struct drm_device *dev)···18171918 /* determine base clock for timer source */2019 if (dev_priv->chipset < 0x40) {2121- n = dev_priv->engine.pm.clock_get(dev, PLL_CORE);2020+ n = nouveau_hw_get_clock(dev, PLL_CORE);2221 } else2322 if (dev_priv->chipset == 0x40) {2423 /*XXX: figure this out */