drm/nv04-nv30/pm: port to newer interfaces

+3 -4

drivers/gpu/drm/nouveau/nouveau_pm.h

··· 47 47 void nouveau_mem_timing_fini(struct drm_device *); 48 48 49 49 /* nv04_pm.c */ 50 - int nv04_pm_clock_get(struct drm_device *, u32 id); 51 - void *nv04_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *, 52 - u32 id, int khz); 53 - void nv04_pm_clock_set(struct drm_device *, void *); 50 + int nv04_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *); 51 + void *nv04_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *); 52 + int nv04_pm_clocks_set(struct drm_device *, void *); 54 53 55 54 /* nv40_pm.c */ 56 55 int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);

+12 -12

drivers/gpu/drm/nouveau/nouveau_state.c

··· 87 87 engine->gpio.get = NULL; 88 88 engine->gpio.set = NULL; 89 89 engine->gpio.irq_enable = NULL; 90 - engine->pm.clock_get = nv04_pm_clock_get; 91 - engine->pm.clock_pre = nv04_pm_clock_pre; 92 - engine->pm.clock_set = nv04_pm_clock_set; 90 + engine->pm.clocks_get = nv04_pm_clocks_get; 91 + engine->pm.clocks_pre = nv04_pm_clocks_pre; 92 + engine->pm.clocks_set = nv04_pm_clocks_set; 93 93 engine->vram.init = nouveau_mem_detect; 94 94 engine->vram.takedown = nouveau_stub_takedown; 95 95 engine->vram.flags_valid = nouveau_mem_flags_valid; ··· 136 136 engine->gpio.get = nv10_gpio_get; 137 137 engine->gpio.set = nv10_gpio_set; 138 138 engine->gpio.irq_enable = NULL; 139 - engine->pm.clock_get = nv04_pm_clock_get; 140 - engine->pm.clock_pre = nv04_pm_clock_pre; 141 - engine->pm.clock_set = nv04_pm_clock_set; 139 + engine->pm.clocks_get = nv04_pm_clocks_get; 140 + engine->pm.clocks_pre = nv04_pm_clocks_pre; 141 + engine->pm.clocks_set = nv04_pm_clocks_set; 142 142 engine->vram.init = nouveau_mem_detect; 143 143 engine->vram.takedown = nouveau_stub_takedown; 144 144 engine->vram.flags_valid = nouveau_mem_flags_valid; ··· 185 185 engine->gpio.get = nv10_gpio_get; 186 186 engine->gpio.set = nv10_gpio_set; 187 187 engine->gpio.irq_enable = NULL; 188 - engine->pm.clock_get = nv04_pm_clock_get; 189 - engine->pm.clock_pre = nv04_pm_clock_pre; 190 - engine->pm.clock_set = nv04_pm_clock_set; 188 + engine->pm.clocks_get = nv04_pm_clocks_get; 189 + engine->pm.clocks_pre = nv04_pm_clocks_pre; 190 + engine->pm.clocks_set = nv04_pm_clocks_set; 191 191 engine->vram.init = nouveau_mem_detect; 192 192 engine->vram.takedown = nouveau_stub_takedown; 193 193 engine->vram.flags_valid = nouveau_mem_flags_valid; ··· 234 234 engine->gpio.get = nv10_gpio_get; 235 235 engine->gpio.set = nv10_gpio_set; 236 236 engine->gpio.irq_enable = NULL; 237 - engine->pm.clock_get = nv04_pm_clock_get; 238 - engine->pm.clock_pre = nv04_pm_clock_pre; 239 - engine->pm.clock_set = nv04_pm_clock_set; 237 + engine->pm.clocks_get = nv04_pm_clocks_get; 238 + engine->pm.clocks_pre = nv04_pm_clocks_pre; 239 + engine->pm.clocks_set = nv04_pm_clocks_set; 240 240 engine->pm.voltage_get = nouveau_voltage_gpio_get; 241 241 engine->pm.voltage_set = nouveau_voltage_gpio_set; 242 242 engine->vram.init = nouveau_mem_detect;

+82 -39

drivers/gpu/drm/nouveau/nv04_pm.c

··· 27 27 #include "nouveau_hw.h" 28 28 #include "nouveau_pm.h" 29 29 30 - struct nv04_pm_state { 30 + int 31 + nv04_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) 32 + { 33 + int ret; 34 + 35 + ret = nouveau_hw_get_clock(dev, PLL_CORE); 36 + if (ret < 0) 37 + return ret; 38 + perflvl->core = ret; 39 + 40 + ret = nouveau_hw_get_clock(dev, PLL_MEMORY); 41 + if (ret < 0) 42 + return ret; 43 + perflvl->memory = ret; 44 + 45 + return 0; 46 + } 47 + 48 + struct nv04_pm_clock { 31 49 struct pll_lims pll; 32 50 struct nouveau_pll_vals calc; 33 51 }; 34 52 35 - int 36 - nv04_pm_clock_get(struct drm_device *dev, u32 id) 53 + struct nv04_pm_state { 54 + struct nv04_pm_clock core; 55 + struct nv04_pm_clock memory; 56 + }; 57 + 58 + static int 59 + calc_pll(struct drm_device *dev, u32 id, int khz, struct nv04_pm_clock *clk) 37 60 { 38 - return nouveau_hw_get_clock(dev, id); 61 + int ret; 62 + 63 + ret = get_pll_limits(dev, id, &clk->pll); 64 + if (ret) 65 + return ret; 66 + 67 + ret = nouveau_calc_pll_mnp(dev, &clk->pll, khz, &clk->calc); 68 + if (!ret) 69 + return -EINVAL; 70 + 71 + return 0; 39 72 } 40 73 41 74 void * 42 - nv04_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, 43 - u32 id, int khz) 75 + nv04_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) 44 76 { 45 - struct nv04_pm_state *state; 77 + struct nv04_pm_state *info; 46 78 int ret; 47 79 48 - state = kzalloc(sizeof(*state), GFP_KERNEL); 49 - if (!state) 80 + info = kzalloc(sizeof(*info), GFP_KERNEL); 81 + if (!info) 50 82 return ERR_PTR(-ENOMEM); 51 83 52 - ret = get_pll_limits(dev, id, &state->pll); 53 - if (ret) { 54 - kfree(state); 55 - return (ret == -ENOENT) ? NULL : ERR_PTR(ret); 84 + ret = calc_pll(dev, PLL_CORE, perflvl->core, &info->core); 85 + if (ret) 86 + goto error; 87 + 88 + if (perflvl->memory) { 89 + ret = calc_pll(dev, PLL_MEMORY, perflvl->memory, &info->memory); 90 + if (ret) 91 + goto error; 56 92 } 57 93 58 - ret = nouveau_calc_pll_mnp(dev, &state->pll, khz, &state->calc); 59 - if (!ret) { 60 - kfree(state); 61 - return ERR_PTR(-EINVAL); 62 - } 63 - 64 - return state; 94 + return info; 95 + error: 96 + kfree(info); 97 + return ERR_PTR(ret); 65 98 } 66 99 67 - void 68 - nv04_pm_clock_set(struct drm_device *dev, void *pre_state) 100 + static void 101 + prog_pll(struct drm_device *dev, struct nv04_pm_clock *clk) 69 102 { 70 103 struct drm_nouveau_private *dev_priv = dev->dev_private; 71 - struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; 72 - struct nv04_pm_state *state = pre_state; 73 - u32 reg = state->pll.reg; 104 + u32 reg = clk->pll.reg; 74 105 75 106 /* thank the insane nouveau_hw_setpll() interface for this */ 76 107 if (dev_priv->card_type >= NV_40) 77 108 reg += 4; 78 109 79 - nouveau_hw_setpll(dev, reg, &state->calc); 80 - 81 - if (dev_priv->card_type < NV_30 && reg == NV_PRAMDAC_MPLL_COEFF) { 82 - if (dev_priv->card_type == NV_20) 83 - nv_mask(dev, 0x1002c4, 0, 1 << 20); 84 - 85 - /* Reset the DLLs */ 86 - nv_mask(dev, 0x1002c0, 0, 1 << 8); 87 - } 88 - 89 - if (reg == NV_PRAMDAC_NVPLL_COEFF) 90 - ptimer->init(dev); 91 - 92 - kfree(state); 110 + nouveau_hw_setpll(dev, reg, &clk->calc); 93 111 } 94 112 113 + int 114 + nv04_pm_clocks_set(struct drm_device *dev, void *pre_state) 115 + { 116 + struct drm_nouveau_private *dev_priv = dev->dev_private; 117 + struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; 118 + struct nv04_pm_state *state = pre_state; 119 + 120 + prog_pll(dev, &state->core); 121 + 122 + if (state->memory.pll.reg) { 123 + prog_pll(dev, &state->memory); 124 + if (dev_priv->card_type < NV_30) { 125 + if (dev_priv->card_type == NV_20) 126 + nv_mask(dev, 0x1002c4, 0, 1 << 20); 127 + 128 + /* Reset the DLLs */ 129 + nv_mask(dev, 0x1002c0, 0, 1 << 8); 130 + } 131 + } 132 + 133 + ptimer->init(dev); 134 + 135 + kfree(state); 136 + return 0; 137 + }