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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: Define the PIPE_CRC_EXP registers
I need a scratch register which fill the following requirements:
- can be accessed via DSB
- all the bits can be read/written
- no serious side effects
So far the only thing I could think of is the "expected CRC"
register. Add the definition so I can use it.
While I only need the hsw+ variant currently, let's define the
older variants as well for completeness.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-7-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
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drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
+47
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
···
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#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
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/* gen2 doesn't have source selection bits */
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#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
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#define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */
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#define PIPE_CRC_EXP_1_MASK_IVB REG_BIT(22, 0) /* ivb */
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#define _PIPE_CRC_EXP_GREEN_A 0x60054
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#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A)
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#define PIPE_CRC_EXP_GREEN_MASK REG_BIT(22, 0) /* pre-ivb */
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#define _PIPE_CRC_EXP_BLUE_A 0x60058
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#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A)
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#define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */
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#define _PIPE_CRC_EXP_RES1_A_I915 0x6005c /* i915+ */
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#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915)
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#define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */
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#define _PIPE_CRC_EXP_RES2_A_G4X 0x60080 /* g4x+ */
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#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X)
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#define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */
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#define _PIPE_CRC_RES_RED_A 0x60060
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#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
···
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#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */
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#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
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/* ivb */
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#define _PIPE_CRC_EXP_2_A_IVB 0x60054
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#define _PIPE_CRC_EXP_2_B_IVB 0x61054
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#define PIPE_CRC_EXP_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
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#define PIPE_CRC_EXP_2_MASK_IVB REG_BIT(22, 0) /* ivb */
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/* ivb */
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#define _PIPE_CRC_EXP_3_A_IVB 0x60058
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#define _PIPE_CRC_EXP_3_B_IVB 0x61058
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#define PIPE_CRC_EXP_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB)
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#define PIPE_CRC_EXP_3_MASK_IVB REG_BIT(22, 0) /* ivb */
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/* ivb */
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#define _PIPE_CRC_EXP_4_A_IVB 0x6005c
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#define _PIPE_CRC_EXP_4_B_IVB 0x6105c
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#define PIPE_CRC_EXP_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
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#define PIPE_CRC_EXP_4_MASK_IVB REG_BIT(22, 0) /* ivb */
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/* ivb */
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#define _PIPE_CRC_EXP_5_A_IVB 0x60060
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#define _PIPE_CRC_EXP_5_B_IVB 0x61060
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#define PIPE_CRC_EXP_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
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#define PIPE_CRC_EXP_5_MASK_IVB REG_BIT(22, 0) /* ivb */
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/* ivb */
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#define _PIPE_CRC_RES_1_A_IVB 0x60064
···
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#define _PIPE_CRC_RES_5_A_IVB 0x60074
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#define _PIPE_CRC_RES_5_B_IVB 0x61074
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#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
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/* hsw+ */
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#define _PIPE_CRC_EXP_A_HSW 0x60054
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#define _PIPE_CRC_EXP_B_HSW 0x61054
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#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
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/* hsw+ */
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#define _PIPE_CRC_RES_A_HSW 0x60064