clk: berlin: drop direct of_iomap of nodes reg property

The Berlin clock driver was sharing a DT node with the pin controller
and the reset driver. All these devices are now sub-nodes of the chip
controller. This patch rework the Berlin clock driver to allow moving
the Berlin clock DT bindings into their own sub-node of the chip
controller node.

Signed-off-by: Antoine Tenart <[e-mail]>
Acked-by: Stephen Boyd <[e-mail]>
Signed-off-by: Sebastian Hesselbarth <[e-mail]>

drivers/clk/berlin/bg2.c

···
 	u8 avpll_flags = 0;
 	int n;
 
-	if (of_device_is_compatible(parent_np, "syscon"))
-		np = parent_np;
-
-	gbase = of_iomap(np, 0);
+	gbase = of_iomap(parent_np, 0);
 	if (!gbase)
 		return;
 
···
 bg2_fail:
 	iounmap(gbase);
 }
-CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl",
-	       berlin2_clock_setup);
-CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
-	       berlin2_clock_setup);
 CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk",
 	       berlin2_clock_setup);

drivers/clk/berlin/bg2q.c

···
 	struct clk *clk;
 	int n;
 
-	if (of_device_is_compatible(parent_np, "syscon"))
-		np = parent_np;
-
-	gbase = of_iomap(np, 0);
+	gbase = of_iomap(parent_np, 0);
 	if (!gbase) {
 		pr_err("%s: Unable to map global base\n", np->full_name);
 		return;
 	}
 
 	/* BG2Q CPU PLL is not part of global registers */
-	cpupll_base = of_iomap(np, 1);
+	cpupll_base = of_iomap(parent_np, 1);
 	if (!cpupll_base) {
 		pr_err("%s: Unable to map cpupll base\n", np->full_name);
 		iounmap(gbase);
···
 	iounmap(cpupll_base);
 	iounmap(gbase);
 }
-CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl",
-	       berlin2q_clock_setup);
 CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
 	       berlin2q_clock_setup);