tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/include:cleanup vega10 header files.

Remove asic_reg/vega10 folder.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Feifei Xu and committed by
Alex Deucher fb960bd2 8af7454e

+36 -36
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 35 35 #include "soc15d.h" 36 36 #include "soc15_common.h" 37 37 38 - #include "vega10/soc15ip.h" 38 + #include "soc15ip.h" 39 39 #include "raven1/VCN/vcn_1_0_offset.h" 40 40 41 41 /* 1 second timeout */
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 28 28 #include "soc15.h" 29 29 #include "soc15d.h" 30 30 31 - #include "vega10/soc15ip.h" 31 + #include "soc15ip.h" 32 32 #include "gc/gc_9_0_offset.h" 33 33 #include "gc/gc_9_0_sh_mask.h" 34 - #include "vega10/vega10_enum.h" 34 + #include "vega10_enum.h" 35 35 #include "hdp/hdp_4_0_offset.h" 36 36 37 37 #include "soc15_common.h"
+2 -2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
··· 23 23 #include "amdgpu.h" 24 24 #include "gfxhub_v1_0.h" 25 25 26 - #include "vega10/soc15ip.h" 26 + #include "soc15ip.h" 27 27 #include "gc/gc_9_0_offset.h" 28 28 #include "gc/gc_9_0_sh_mask.h" 29 29 #include "gc/gc_9_0_default.h" 30 - #include "vega10/vega10_enum.h" 30 + #include "vega10_enum.h" 31 31 32 32 #include "soc15_common.h" 33 33
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 25 25 #include "gmc_v9_0.h" 26 26 #include "amdgpu_atomfirmware.h" 27 27 28 - #include "vega10/soc15ip.h" 28 + #include "soc15ip.h" 29 29 #include "hdp/hdp_4_0_offset.h" 30 30 #include "hdp/hdp_4_0_sh_mask.h" 31 31 #include "gc/gc_9_0_sh_mask.h" 32 32 #include "dce/dce_12_0_offset.h" 33 33 #include "dce/dce_12_0_sh_mask.h" 34 - #include "vega10/vega10_enum.h" 34 + #include "vega10_enum.h" 35 35 #include "mmhub/mmhub_1_0_offset.h" 36 36 #include "athub/athub_1_0_offset.h" 37 37
+2 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
··· 23 23 #include "amdgpu.h" 24 24 #include "mmhub_v1_0.h" 25 25 26 - #include "vega10/soc15ip.h" 26 + #include "soc15ip.h" 27 27 #include "mmhub/mmhub_1_0_offset.h" 28 28 #include "mmhub/mmhub_1_0_sh_mask.h" 29 29 #include "mmhub/mmhub_1_0_default.h" 30 30 #include "athub/athub_1_0_offset.h" 31 31 #include "athub/athub_1_0_sh_mask.h" 32 - #include "vega10/vega10_enum.h" 32 + #include "vega10_enum.h" 33 33 34 34 #include "soc15_common.h" 35 35
+1 -1
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
··· 22 22 */ 23 23 24 24 #include "amdgpu.h" 25 - #include "vega10/soc15ip.h" 25 + #include "soc15ip.h" 26 26 #include "nbio/nbio_6_1_offset.h" 27 27 #include "nbio/nbio_6_1_sh_mask.h" 28 28 #include "gc/gc_9_0_offset.h"
+2 -2
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
··· 24 24 #include "amdgpu_atombios.h" 25 25 #include "nbio_v6_1.h" 26 26 27 - #include "vega10/soc15ip.h" 27 + #include "soc15ip.h" 28 28 #include "nbio/nbio_6_1_default.h" 29 29 #include "nbio/nbio_6_1_offset.h" 30 30 #include "nbio/nbio_6_1_sh_mask.h" 31 - #include "vega10/vega10_enum.h" 31 + #include "vega10_enum.h" 32 32 33 33 #define smnCPM_CONTROL 0x11180460 34 34 #define smnPCIE_CNTL2 0x11180070
+2 -2
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
··· 24 24 #include "amdgpu_atombios.h" 25 25 #include "nbio_v7_0.h" 26 26 27 - #include "vega10/soc15ip.h" 27 + #include "soc15ip.h" 28 28 #include "raven1/NBIO/nbio_7_0_default.h" 29 29 #include "raven1/NBIO/nbio_7_0_offset.h" 30 30 #include "raven1/NBIO/nbio_7_0_sh_mask.h" 31 - #include "vega10/vega10_enum.h" 31 + #include "vega10_enum.h" 32 32 33 33 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c 34 34
+1 -1
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
··· 30 30 #include "soc15_common.h" 31 31 #include "psp_v10_0.h" 32 32 33 - #include "vega10/soc15ip.h" 33 + #include "soc15ip.h" 34 34 #include "raven1/MP/mp_10_0_offset.h" 35 35 #include "raven1/GC/gc_9_1_offset.h" 36 36 #include "raven1/SDMA0/sdma0_4_1_offset.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
··· 31 31 #include "soc15_common.h" 32 32 #include "psp_v3_1.h" 33 33 34 - #include "vega10/soc15ip.h" 34 + #include "soc15ip.h" 35 35 #include "mp/mp_9_0_offset.h" 36 36 #include "mp/mp_9_0_sh_mask.h" 37 37 #include "gc/gc_9_0_offset.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 27 27 #include "amdgpu_ucode.h" 28 28 #include "amdgpu_trace.h" 29 29 30 - #include "vega10/soc15ip.h" 30 + #include "soc15ip.h" 31 31 #include "sdma0/sdma0_4_0_offset.h" 32 32 #include "sdma0/sdma0_4_0_sh_mask.h" 33 33 #include "sdma1/sdma1_4_0_offset.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 34 34 #include "atom.h" 35 35 #include "amd_pcie.h" 36 36 37 - #include "vega10/soc15ip.h" 37 + #include "soc15ip.h" 38 38 #include "uvd/uvd_7_0_offset.h" 39 39 #include "gc/gc_9_0_offset.h" 40 40 #include "gc/gc_9_0_sh_mask.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
··· 29 29 #include "soc15_common.h" 30 30 #include "mmsch_v1_0.h" 31 31 32 - #include "vega10/soc15ip.h" 32 + #include "soc15ip.h" 33 33 #include "uvd/uvd_7_0_offset.h" 34 34 #include "uvd/uvd_7_0_sh_mask.h" 35 35 #include "vce/vce_4_0_offset.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 32 32 #include "soc15_common.h" 33 33 #include "mmsch_v1_0.h" 34 34 35 - #include "vega10/soc15ip.h" 35 + #include "soc15ip.h" 36 36 #include "vce/vce_4_0_offset.h" 37 37 #include "vce/vce_4_0_default.h" 38 38 #include "vce/vce_4_0_sh_mask.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 28 28 #include "soc15d.h" 29 29 #include "soc15_common.h" 30 30 31 - #include "vega10/soc15ip.h" 31 + #include "soc15ip.h" 32 32 #include "raven1/VCN/vcn_1_0_offset.h" 33 33 #include "raven1/VCN/vcn_1_0_sh_mask.h" 34 34 #include "hdp/hdp_4_0_offset.h"
+1 -1
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
··· 26 26 #include "soc15.h" 27 27 28 28 29 - #include "vega10/soc15ip.h" 29 + #include "soc15ip.h" 30 30 #include "oss/osssys_4_0_offset.h" 31 31 #include "oss/osssys_4_0_sh_mask.h" 32 32
+1 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 61 61 62 62 #include "raven1/DCN/dcn_1_0_offset.h" 63 63 #include "raven1/DCN/dcn_1_0_sh_mask.h" 64 - #include "vega10/soc15ip.h" 64 + #include "soc15ip.h" 65 65 66 66 #include "soc15_common.h" 67 67 #endif
+1 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
··· 33 33 34 34 #include "dce/dce_12_0_offset.h" 35 35 #include "dce/dce_12_0_sh_mask.h" 36 - #include "vega10/soc15ip.h" 36 + #include "soc15ip.h" 37 37 #include "reg_helper.h" 38 38 39 39 #define CTX \
+1 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
··· 56 56 57 57 #include "dce/dce_12_0_offset.h" 58 58 #include "dce/dce_12_0_sh_mask.h" 59 - #include "vega10/soc15ip.h" 59 + #include "soc15ip.h" 60 60 #include "nbio/nbio_6_1_offset.h" 61 61 #include "reg_helper.h" 62 62
+1 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
··· 27 27 28 28 #include "dce/dce_12_0_offset.h" 29 29 #include "dce/dce_12_0_sh_mask.h" 30 - #include "vega10/soc15ip.h" 30 + #include "soc15ip.h" 31 31 32 32 #include "dc_types.h" 33 33 #include "dc_bios_types.h"
+1 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
··· 50 50 #include "dcn10_hubp.h" 51 51 #include "dcn10_hubbub.h" 52 52 53 - #include "vega10/soc15ip.h" 53 + #include "soc15ip.h" 54 54 55 55 #include "raven1/DCN/dcn_1_0_offset.h" 56 56 #include "raven1/DCN/dcn_1_0_sh_mask.h"
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
··· 36 36 37 37 #include "dce/dce_12_0_offset.h" 38 38 #include "dce/dce_12_0_sh_mask.h" 39 - #include "vega10/soc15ip.h" 39 + #include "soc15ip.h" 40 40 41 41 #define block HPD 42 42 #define reg_num 0
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
··· 35 35 36 36 #include "dce/dce_12_0_offset.h" 37 37 #include "dce/dce_12_0_sh_mask.h" 38 - #include "vega10/soc15ip.h" 38 + #include "soc15ip.h" 39 39 40 40 /* begin ********************* 41 41 * macros to expend register list macro defined in HW object header file */
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
··· 36 36 37 37 #include "raven1/DCN/dcn_1_0_offset.h" 38 38 #include "raven1/DCN/dcn_1_0_sh_mask.h" 39 - #include "vega10/soc15ip.h" 39 + #include "soc15ip.h" 40 40 41 41 #define block HPD 42 42 #define reg_num 0
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
··· 35 35 36 36 #include "raven1/DCN/dcn_1_0_offset.h" 37 37 #include "raven1/DCN/dcn_1_0_sh_mask.h" 38 - #include "vega10/soc15ip.h" 38 + #include "soc15ip.h" 39 39 40 40 /* begin ********************* 41 41 * macros to expend register list macro defined in HW object header file */
+1 -1
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
··· 38 38 39 39 #include "dce/dce_12_0_offset.h" 40 40 #include "dce/dce_12_0_sh_mask.h" 41 - #include "vega10/soc15ip.h" 41 + #include "soc15ip.h" 42 42 43 43 /* begin ********************* 44 44 * macros to expend register list macro defined in HW object header file */
+1 -1
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
··· 38 38 39 39 #include "raven1/DCN/dcn_1_0_offset.h" 40 40 #include "raven1/DCN/dcn_1_0_sh_mask.h" 41 - #include "vega10/soc15ip.h" 41 + #include "soc15ip.h" 42 42 43 43 /* begin ********************* 44 44 * macros to expend register list macro defined in HW object header file */
+1 -1
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
··· 32 32 33 33 #include "dce/dce_12_0_offset.h" 34 34 #include "dce/dce_12_0_sh_mask.h" 35 - #include "vega10/soc15ip.h" 35 + #include "soc15ip.h" 36 36 37 37 #include "ivsrcid/ivsrcid_vislands30.h" 38 38
+1 -1
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
··· 31 31 32 32 #include "raven1/DCN/dcn_1_0_offset.h" 33 33 #include "raven1/DCN/dcn_1_0_sh_mask.h" 34 - #include "vega10/soc15ip.h" 34 + #include "soc15ip.h" 35 35 36 36 #include "irq_service_dcn10.h" 37 37
drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h drivers/gpu/drm/amd/include/soc15ip.h
drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h drivers/gpu/drm/amd/include/vega10_enum.h
+1 -1
drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
··· 23 23 #ifndef PP_SOC15_H 24 24 #define PP_SOC15_H 25 25 26 - #include "vega10/soc15ip.h" 26 + #include "soc15ip.h" 27 27 28 28 inline static uint32_t soc15_get_register_offset( 29 29 uint32_t hw_id,