tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/include:cleanup vega10 osssys header files.
Cleanup asic_reg/vega10/OSSSYS folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Feifei Xu
and committed by
Alex Deucher
8af7454e
424d9bb4
+2
-178
+2
-2
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
-176
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
-176
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
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/*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _osssys_4_0_DEFAULT_HEADER
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#define _osssys_4_0_DEFAULT_HEADER
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// addressBlock: osssys_osssysdec
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#define mmIH_VMID_0_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_1_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_2_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_3_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_4_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_5_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_6_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_7_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_8_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_9_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_10_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_11_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_12_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_13_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_14_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_15_LUT_DEFAULT 0x00000000
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#define mmIH_VMID_0_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_1_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_2_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_3_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_4_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_5_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_6_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_7_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_8_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_9_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_10_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_11_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_12_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_13_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_14_LUT_MM_DEFAULT 0x00000000
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#define mmIH_VMID_15_LUT_MM_DEFAULT 0x00000000
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#define mmIH_COOKIE_0_DEFAULT 0x00000000
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#define mmIH_COOKIE_1_DEFAULT 0x00000000
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#define mmIH_COOKIE_2_DEFAULT 0x00000000
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#define mmIH_COOKIE_3_DEFAULT 0x00000000
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#define mmIH_COOKIE_4_DEFAULT 0x00000000
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#define mmIH_COOKIE_5_DEFAULT 0x00000000
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#define mmIH_COOKIE_6_DEFAULT 0x00000000
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#define mmIH_COOKIE_7_DEFAULT 0x00000000
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#define mmIH_REGISTER_LAST_PART0_DEFAULT 0x00000000
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#define mmSEM_REQ_INPUT_0_DEFAULT 0x00000000
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#define mmSEM_REQ_INPUT_1_DEFAULT 0x00000000
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#define mmSEM_REQ_INPUT_2_DEFAULT 0x00000000
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#define mmSEM_REQ_INPUT_3_DEFAULT 0x00000000
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#define mmSEM_REGISTER_LAST_PART0_DEFAULT 0x00000000
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#define mmIH_RB_CNTL_DEFAULT 0x10610000
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#define mmIH_RB_BASE_DEFAULT 0x00000000
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#define mmIH_RB_BASE_HI_DEFAULT 0x00000000
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#define mmIH_RB_RPTR_DEFAULT 0x00000000
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#define mmIH_RB_WPTR_DEFAULT 0x00000000
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#define mmIH_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
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#define mmIH_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
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#define mmIH_DOORBELL_RPTR_DEFAULT 0x00000000
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#define mmIH_RB_CNTL_RING1_DEFAULT 0x10410000
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#define mmIH_RB_BASE_RING1_DEFAULT 0x00000000
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#define mmIH_RB_BASE_HI_RING1_DEFAULT 0x00000000
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#define mmIH_RB_RPTR_RING1_DEFAULT 0x00000000
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#define mmIH_RB_WPTR_RING1_DEFAULT 0x00000000
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#define mmIH_DOORBELL_RPTR_RING1_DEFAULT 0x00000000
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#define mmIH_RB_CNTL_RING2_DEFAULT 0x10410000
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#define mmIH_RB_BASE_RING2_DEFAULT 0x00000000
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#define mmIH_RB_BASE_HI_RING2_DEFAULT 0x00000000
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#define mmIH_RB_RPTR_RING2_DEFAULT 0x00000000
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#define mmIH_RB_WPTR_RING2_DEFAULT 0x00000000
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#define mmIH_DOORBELL_RPTR_RING2_DEFAULT 0x00000000
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#define mmIH_VERSION_DEFAULT 0x00000400
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#define mmIH_CNTL_DEFAULT 0x01000000
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#define mmIH_CNTL2_DEFAULT 0x000000ff
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#define mmIH_STATUS_DEFAULT 0x00040847
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#define mmIH_PERFMON_CNTL_DEFAULT 0x00000000
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#define mmIH_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
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#define mmIH_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
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#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT 0x00000000
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#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT 0x00000000
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#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT 0x00000000
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#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT 0x0000007f
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#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT 0x0fffffff
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#define mmIH_DSM_MATCH_FCN_ID_DEFAULT 0x00000000
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#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT 0x00000000
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#define mmIH_VF_RB_STATUS_DEFAULT 0x00000000
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#define mmIH_VF_RB_STATUS2_DEFAULT 0x00000000
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#define mmIH_VF_RB1_STATUS_DEFAULT 0x00000000
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#define mmIH_VF_RB1_STATUS2_DEFAULT 0x00000000
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#define mmIH_VF_RB2_STATUS_DEFAULT 0x00000000
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#define mmIH_VF_RB2_STATUS2_DEFAULT 0x00000000
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#define mmIH_INT_FLOOD_CNTL_DEFAULT 0x00000000
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#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT 0x00000000
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#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT 0x00000000
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#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT 0x00000000
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#define mmIH_INT_FLOOD_STATUS_DEFAULT 0x00000000
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#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT 0x00000000
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#define mmIH_CLK_CTRL_DEFAULT 0x00000000
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#define mmIH_INT_FLAGS_DEFAULT 0x00000000
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#define mmIH_LAST_INT_INFO0_DEFAULT 0x00000000
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#define mmIH_LAST_INT_INFO1_DEFAULT 0x00000000
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#define mmIH_LAST_INT_INFO2_DEFAULT 0x00000000
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#define mmIH_SCRATCH_DEFAULT 0x00000000
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#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT 0x00000000
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#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
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#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT 0x00000000
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#define mmIH_CREDIT_STATUS_DEFAULT 0xfffffffe
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#define mmIH_MMHUB_ERROR_DEFAULT 0x00000000
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#define mmIH_REGISTER_LAST_PART2_DEFAULT 0x00000000
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#define mmSEM_CLK_CTRL_DEFAULT 0x00000100
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#define mmSEM_UTC_CREDIT_DEFAULT 0x00000510
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#define mmSEM_UTC_CONFIG_DEFAULT 0x00000020
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#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT 0x800000ff
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#define mmSEM_MCIF_CONFIG_DEFAULT 0x00001040
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#define mmSEM_PERFMON_CNTL_DEFAULT 0x00000000
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#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
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#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
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#define mmSEM_STATUS_DEFAULT 0x80f90003
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#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT 0x00fac688
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#define mmSEM_MAILBOX_DEFAULT 0x00000000
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#define mmSEM_MAILBOX_CONTROL_DEFAULT 0x00000000
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#define mmSEM_CHICKEN_BITS_DEFAULT 0x00084ad6
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#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT 0x00000008
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#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
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#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT 0x00000010
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#define mmSEM_REGISTER_LAST_PART2_DEFAULT 0x00000000
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#define mmIH_ACTIVE_FCN_ID_DEFAULT 0x00000000
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#define mmIH_VIRT_RESET_REQ_DEFAULT 0x00000000
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#define mmIH_CLIENT_CFG_DEFAULT 0x0000001f
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#define mmIH_CLIENT_CFG_INDEX_DEFAULT 0x00000000
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#define mmIH_CLIENT_CFG_DATA_DEFAULT 0x00000000
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#define mmIH_CID_REMAP_INDEX_DEFAULT 0x00000000
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#define mmIH_CID_REMAP_DATA_DEFAULT 0x00000000
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#define mmIH_CHICKEN_DEFAULT 0x00000000
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#define mmIH_MMHUB_CNTL_DEFAULT 0x00000001
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#define mmIH_REGISTER_LAST_PART1_DEFAULT 0x00000000
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#define mmSEM_ACTIVE_FCN_ID_DEFAULT 0x00000000
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#define mmSEM_VIRT_RESET_REQ_DEFAULT 0x00000000
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#define mmSEM_RESP_SDMA0_DEFAULT 0x0004950c
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#define mmSEM_RESP_SDMA1_DEFAULT 0x0004958c
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#define mmSEM_RESP_UVD_DEFAULT 0x0004860c
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#define mmSEM_RESP_VCE_0_DEFAULT 0x0004900c
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#define mmSEM_RESP_ACP_DEFAULT 0x0004870c
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#define mmSEM_RESP_ISP_DEFAULT 0x00000000
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#define mmSEM_RESP_VCE_1_DEFAULT 0x0004908c
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#define mmSEM_RESP_VP8_DEFAULT 0x00000000
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#define mmSEM_RESP_GC_DEFAULT 0x0004858c
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#define mmSEM_CID_REMAP_INDEX_DEFAULT 0x00000000
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#define mmSEM_CID_REMAP_DATA_DEFAULT 0x00000000
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#define mmSEM_ATOMIC_OP_LUT_DEFAULT 0x040a102f
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#define mmSEM_EDC_CONFIG_DEFAULT 0x00000002
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#define mmSEM_CHICKEN_BITS2_DEFAULT 0x00000000
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#define mmSEM_MMHUB_CNTL_DEFAULT 0x00000000
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#define mmSEM_REGISTER_LAST_PART1_DEFAULT 0x00000000
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#endif
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h