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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'pinctrl-v6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Fixes two issues with the Qualcomm SA8775P platform:
- Some minor device tree binding flunky that is nice to iron out but
more importantly:
- Support the increased interrupt targets mask from 3 to 4 bits,
making interrupts with higher (hardware) numbers work"
* tag 'pinctrl-v6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets
dt-bindings: pinctrl: qcom,sa8775p-tlmm: add gpio function constant
+10
-4
+1
-1
Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
···
87
87
emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
88
88
emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
89
89
emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
90
-
gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
90
+
gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
91
91
jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
92
92
mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
93
93
mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
+6
-3
drivers/pinctrl/qcom/pinctrl-msm.c
+6
-3
drivers/pinctrl/qcom/pinctrl-msm.c
···
1038
1038
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1039
1039
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1040
1040
const struct msm_pingroup *g;
1041
+
u32 intr_target_mask = GENMASK(2, 0);
1041
1042
unsigned long flags;
1042
1043
bool was_enabled;
1043
1044
u32 val;
···
1075
1074
* With intr_target_use_scm interrupts are routed to
1076
1075
* application cpu using scm calls.
1077
1076
*/
1077
+
if (g->intr_target_width)
1078
+
intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
1079
+
1078
1080
if (pctrl->intr_target_use_scm) {
1079
1081
u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1080
1082
int ret;
1081
1083
1082
1084
qcom_scm_io_readl(addr, &val);
1083
-
1084
-
val &= ~(7 << g->intr_target_bit);
1085
+
val &= ~(intr_target_mask << g->intr_target_bit);
1085
1086
val |= g->intr_target_kpss_val << g->intr_target_bit;
1086
1087
1087
1088
ret = qcom_scm_io_writel(addr, val);
···
1093
1090
d->hwirq);
1094
1091
} else {
1095
1092
val = msm_readl_intr_target(pctrl, g);
1096
-
val &= ~(7 << g->intr_target_bit);
1093
+
val &= ~(intr_target_mask << g->intr_target_bit);
1097
1094
val |= g->intr_target_kpss_val << g->intr_target_bit;
1098
1095
msm_writel_intr_target(val, pctrl, g);
1099
1096
}
+2
drivers/pinctrl/qcom/pinctrl-msm.h
+2
drivers/pinctrl/qcom/pinctrl-msm.h
···
59
59
* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
60
60
* status.
61
61
* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
62
+
* @intr_target_width: Number of bits used for specifying interrupt routing target.
62
63
* @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
63
64
* this gpio should get routed to the KPSS processor.
64
65
* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
···
101
100
unsigned intr_ack_high:1;
102
101
103
102
unsigned intr_target_bit:5;
103
+
unsigned intr_target_width:5;
104
104
unsigned intr_target_kpss_val:5;
105
105
unsigned intr_raw_status_bit:5;
106
106
unsigned intr_polarity_bit:5;