tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"As usual, mostly DT fixes for the major Arm platforms from Qualcomm
and NXP, plus a bit for Rockchips and others:

The qualcomm fixes mainly deal with their higher-end arm64 devices
trees, fixing issues in L3 interconnect, crypto, thermal, UFS and a
regression for the DSI phy.

NXP i.MX has two correctness fixes for the 64-bit chips, dealing with
the imx93 "anatop" module and the CSI interface. On the 32-bit side,
there are functional fixes for RTC, display and SD card intefaces.

Rockchip fixes are for wifi support on certain boards, a eMMC
stability and DT build warnings.

On TI OMAP, a regulator is described in DT to avoid problems with the
ethernet phy initialization.

The code changes include a missing MMIO serialization on OMAP, plus a
few minor fixes on ASpeed and AMD/Zynq chips"

* tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (30 commits)
ARM: dts: am335x-bone-common: Add vcc-supply for on-board eeprom
ARM: dts: am335x-bone-common: Add GPIO PHY reset on revision C3 board
soc: aspeed: socinfo: Add kfree for kstrdup
soc: aspeed: uart-routing: Use __sysfs_match_string
ARM: dts: integrator: fix PCI bus dtc warnings
arm64: dts: imx93: Fix anatop node size
arm64: dts: qcom: sc7180: Fix DSI0_PHY reg-names
ARM: dts: imx: Set default tuning step for imx6sx usdhc
arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration
arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
ARM: dts: imx: Set default tuning step for imx7d usdhc
ARM: dts: imx6: phytec: fix RTC interrupt level
ARM: dts: imx6sx: Remove LDB endpoint
arm64: dts: rockchip: Fix Wifi/Bluetooth on ROCK Pi 4 boards
ARM: zynq: Explicitly include correct DT includes
arm64: dts: qcom: sa8775p-ride: Update L4C parameters
arm64: dts: rockchip: minor whitespace cleanup around '='
arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+
arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4
arm64: dts: rockchip: add missing space before { on indiedroid nova
...

Linus Torvalds 80706f55 eabeef90

+86 -112
+1 -1
arch/arm/boot/dts/arm/integratorap.dts
··· 158 158 valid-mask = <0x003fffff>; 159 159 }; 160 160 161 - pci: pciv3@62000000 { 161 + pci: pci@62000000 { 162 162 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; 163 163 device_type = "pci"; 164 164 #interrupt-cells = <1>;
+1 -1
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
··· 182 182 pinctrl-0 = <&pinctrl_rtc_int>; 183 183 reg = <0x68>; 184 184 interrupt-parent = <&gpio7>; 185 - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 185 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 186 186 status = "disabled"; 187 187 }; 188 188 };
+8 -6
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
··· 863 863 reg = <0>; 864 864 865 865 ldb_from_lcdif1: endpoint { 866 - remote-endpoint = <&lcdif1_to_ldb>; 867 866 }; 868 867 }; 869 868 ··· 1009 1010 <&clks IMX6SX_CLK_USDHC1>; 1010 1011 clock-names = "ipg", "ahb", "per"; 1011 1012 bus-width = <4>; 1013 + fsl,tuning-start-tap = <20>; 1014 + fsl,tuning-step= <2>; 1012 1015 status = "disabled"; 1013 1016 }; 1014 1017 ··· 1023 1022 <&clks IMX6SX_CLK_USDHC2>; 1024 1023 clock-names = "ipg", "ahb", "per"; 1025 1024 bus-width = <4>; 1025 + fsl,tuning-start-tap = <20>; 1026 + fsl,tuning-step= <2>; 1026 1027 status = "disabled"; 1027 1028 }; 1028 1029 ··· 1037 1034 <&clks IMX6SX_CLK_USDHC3>; 1038 1035 clock-names = "ipg", "ahb", "per"; 1039 1036 bus-width = <4>; 1037 + fsl,tuning-start-tap = <20>; 1038 + fsl,tuning-step= <2>; 1040 1039 status = "disabled"; 1041 1040 }; 1042 1041 ··· 1314 1309 power-domains = <&pd_disp>; 1315 1310 status = "disabled"; 1316 1311 1317 - ports { 1318 - port { 1319 - lcdif1_to_ldb: endpoint { 1320 - remote-endpoint = <&ldb_from_lcdif1>; 1321 - }; 1312 + port { 1313 + lcdif1_to_ldb: endpoint { 1322 1314 }; 1323 1315 }; 1324 1316 };
+6
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
··· 1184 1184 <&clks IMX7D_USDHC1_ROOT_CLK>; 1185 1185 clock-names = "ipg", "ahb", "per"; 1186 1186 bus-width = <4>; 1187 + fsl,tuning-step = <2>; 1188 + fsl,tuning-start-tap = <20>; 1187 1189 status = "disabled"; 1188 1190 }; 1189 1191 ··· 1198 1196 <&clks IMX7D_USDHC2_ROOT_CLK>; 1199 1197 clock-names = "ipg", "ahb", "per"; 1200 1198 bus-width = <4>; 1199 + fsl,tuning-step = <2>; 1200 + fsl,tuning-start-tap = <20>; 1201 1201 status = "disabled"; 1202 1202 }; 1203 1203 ··· 1212 1208 <&clks IMX7D_USDHC3_ROOT_CLK>; 1213 1209 clock-names = "ipg", "ahb", "per"; 1214 1210 bus-width = <4>; 1211 + fsl,tuning-step = <2>; 1212 + fsl,tuning-start-tap = <20>; 1215 1213 status = "disabled"; 1216 1214 }; 1217 1215
+9
arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
··· 145 145 /* MDIO */ 146 146 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 147 147 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 148 + /* Added to support GPIO controlled PHY reset */ 149 + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7) 148 150 >; 149 151 }; 150 152 ··· 155 153 /* MDIO reset value */ 156 154 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 157 155 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 156 + /* Added to support GPIO controlled PHY reset */ 157 + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 158 158 >; 159 159 }; 160 160 ··· 219 215 baseboard_eeprom: baseboard_eeprom@50 { 220 216 compatible = "atmel,24c256"; 221 217 reg = <0x50>; 218 + vcc-supply = <&ldo4_reg>; 222 219 223 220 #address-cells = <1>; 224 221 #size-cells = <1>; ··· 382 377 383 378 ethphy0: ethernet-phy@0 { 384 379 reg = <0>; 380 + /* Support GPIO reset on revision C3 boards */ 381 + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 382 + reset-assert-us = <300>; 383 + reset-deassert-us = <6500>; 385 384 }; 386 385 }; 387 386
+1 -1
arch/arm/mach-zynq/pm.c
··· 8 8 */ 9 9 10 10 #include <linux/io.h> 11 + #include <linux/of.h> 11 12 #include <linux/of_address.h> 12 - #include <linux/of_device.h> 13 13 #include "common.h" 14 14 15 15 /* register offsets */
+3 -4
arch/arm64/boot/dts/freescale/imx8mm.dtsi
··· 1221 1221 compatible = "fsl,imx8mm-mipi-csi2"; 1222 1222 reg = <0x32e30000 0x1000>; 1223 1223 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1224 - assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, 1225 - <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1226 - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 1227 - <&clk IMX8MM_SYS_PLL2_1000M>; 1224 + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; 1225 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; 1226 + 1228 1227 clock-frequency = <333000000>; 1229 1228 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1230 1229 <&clk IMX8MM_CLK_CSI1_ROOT>,
+2 -4
arch/arm64/boot/dts/freescale/imx8mn.dtsi
··· 1175 1175 compatible = "fsl,imx8mm-mipi-csi2"; 1176 1176 reg = <0x32e30000 0x1000>; 1177 1177 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1178 - assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, 1179 - <&clk IMX8MN_CLK_CSI1_PHY_REF>; 1180 - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, 1181 - <&clk IMX8MN_SYS_PLL2_1000M>; 1178 + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; 1179 + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; 1182 1180 assigned-clock-rates = <333000000>; 1183 1181 clock-frequency = <333000000>; 1184 1182 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+1 -1
arch/arm64/boot/dts/freescale/imx93.dtsi
··· 340 340 341 341 anatop: anatop@44480000 { 342 342 compatible = "fsl,imx93-anatop", "syscon"; 343 - reg = <0x44480000 0x10000>; 343 + reg = <0x44480000 0x2000>; 344 344 }; 345 345 346 346 adc1: adc@44530000 {
+1 -1
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
··· 121 121 }; 122 122 }; 123 123 124 - pm8150l-thermal { 124 + pm8150l-pcb-thermal { 125 125 polling-delay-passive = <0>; 126 126 polling-delay = <0>; 127 127 thermal-sensors = <&pm8150l_adc_tm 1>;
+2 -2
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
··· 153 153 154 154 vreg_l4c: ldo4 { 155 155 regulator-name = "vreg_l4c"; 156 - regulator-min-microvolt = <1100000>; 157 - regulator-max-microvolt = <1300000>; 156 + regulator-min-microvolt = <1200000>; 157 + regulator-max-microvolt = <1200000>; 158 158 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 159 159 /* 160 160 * FIXME: This should have regulator-allow-set-load but
+2 -2
arch/arm64/boot/dts/qcom/sc7180.dtsi
··· 3120 3120 reg = <0 0x0ae94400 0 0x200>, 3121 3121 <0 0x0ae94600 0 0x280>, 3122 3122 <0 0x0ae94a00 0 0x1e0>; 3123 - reg-names = "dsi0_phy", 3124 - "dsi0_phy_lane", 3123 + reg-names = "dsi_phy", 3124 + "dsi_phy_lane", 3125 3125 "dsi_pll"; 3126 3126 3127 3127 #clock-cells = <1>;
+1 -1
arch/arm64/boot/dts/qcom/sc8180x.dtsi
··· 3561 3561 }; 3562 3562 3563 3563 osm_l3: interconnect@18321000 { 3564 - compatible = "qcom,sc8180x-osm-l3"; 3564 + compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3565 3565 reg = <0 0x18321000 0 0x1400>; 3566 3566 3567 3567 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+9 -9
arch/arm64/boot/dts/qcom/sm8150.dtsi
··· 56 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 57 operating-points-v2 = <&cpu0_opp_table>; 58 58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 59 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 59 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 60 power-domains = <&CPU_PD0>; 61 61 power-domain-names = "psci"; 62 62 #cooling-cells = <2>; ··· 85 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 86 operating-points-v2 = <&cpu0_opp_table>; 87 87 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 88 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 88 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 89 power-domains = <&CPU_PD1>; 90 90 power-domain-names = "psci"; 91 91 #cooling-cells = <2>; ··· 109 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 110 operating-points-v2 = <&cpu0_opp_table>; 111 111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 112 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 112 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113 113 power-domains = <&CPU_PD2>; 114 114 power-domain-names = "psci"; 115 115 #cooling-cells = <2>; ··· 133 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 134 operating-points-v2 = <&cpu0_opp_table>; 135 135 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 136 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 136 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 137 power-domains = <&CPU_PD3>; 138 138 power-domain-names = "psci"; 139 139 #cooling-cells = <2>; ··· 157 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 158 operating-points-v2 = <&cpu4_opp_table>; 159 159 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 160 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 160 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 161 power-domains = <&CPU_PD4>; 162 162 power-domain-names = "psci"; 163 163 #cooling-cells = <2>; ··· 181 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 182 operating-points-v2 = <&cpu4_opp_table>; 183 183 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 184 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 184 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 185 power-domains = <&CPU_PD5>; 186 186 power-domain-names = "psci"; 187 187 #cooling-cells = <2>; ··· 205 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 206 operating-points-v2 = <&cpu4_opp_table>; 207 207 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 208 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 208 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 209 power-domains = <&CPU_PD6>; 210 210 power-domain-names = "psci"; 211 211 #cooling-cells = <2>; ··· 229 229 qcom,freq-domain = <&cpufreq_hw 2>; 230 230 operating-points-v2 = <&cpu7_opp_table>; 231 231 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 232 - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; 232 + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233 233 power-domains = <&CPU_PD7>; 234 234 power-domain-names = "psci"; 235 235 #cooling-cells = <2>; ··· 4342 4342 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4343 4343 clock-names = "xo", "alternate"; 4344 4344 4345 - #interconnect-cells = <2>; 4345 + #interconnect-cells = <1>; 4346 4346 }; 4347 4347 4348 4348 cpufreq_hw: cpufreq@18323000 {
+9 -9
arch/arm64/boot/dts/qcom/sm8250.dtsi
··· 107 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 108 operating-points-v2 = <&cpu0_opp_table>; 109 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 110 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 110 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 111 111 #cooling-cells = <2>; 112 112 L2_0: l2-cache { 113 113 compatible = "cache"; ··· 138 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 139 operating-points-v2 = <&cpu0_opp_table>; 140 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 141 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 142 142 #cooling-cells = <2>; 143 143 L2_100: l2-cache { 144 144 compatible = "cache"; ··· 163 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 164 operating-points-v2 = <&cpu0_opp_table>; 165 165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 166 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 166 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 167 167 #cooling-cells = <2>; 168 168 L2_200: l2-cache { 169 169 compatible = "cache"; ··· 188 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 189 operating-points-v2 = <&cpu0_opp_table>; 190 190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 191 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 191 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 192 192 #cooling-cells = <2>; 193 193 L2_300: l2-cache { 194 194 compatible = "cache"; ··· 213 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 214 operating-points-v2 = <&cpu4_opp_table>; 215 215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 216 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 216 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 217 217 #cooling-cells = <2>; 218 218 L2_400: l2-cache { 219 219 compatible = "cache"; ··· 238 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 239 operating-points-v2 = <&cpu4_opp_table>; 240 240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 241 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 241 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 242 242 #cooling-cells = <2>; 243 243 L2_500: l2-cache { 244 244 compatible = "cache"; ··· 263 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 264 operating-points-v2 = <&cpu4_opp_table>; 265 265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 266 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 266 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 267 267 #cooling-cells = <2>; 268 268 L2_600: l2-cache { 269 269 compatible = "cache"; ··· 288 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 289 operating-points-v2 = <&cpu7_opp_table>; 290 290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 291 - <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; 291 + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 292 292 #cooling-cells = <2>; 293 293 L2_700: l2-cache { 294 294 compatible = "cache"; ··· 5679 5679 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5680 5680 clock-names = "xo", "alternate"; 5681 5681 5682 - #interconnect-cells = <2>; 5682 + #interconnect-cells = <1>; 5683 5683 }; 5684 5684 5685 5685 cpufreq_hw: cpufreq@18591000 {
+4
arch/arm64/boot/dts/qcom/sm8350.dtsi
··· 1744 1744 qcom,controlled-remotely; 1745 1745 iommus = <&apps_smmu 0x594 0x0011>, 1746 1746 <&apps_smmu 0x596 0x0011>; 1747 + /* FIXME: Probing BAM DMA causes some abort and system hang */ 1748 + status = "fail"; 1747 1749 }; 1748 1750 1749 1751 crypto: crypto@1dfa000 { ··· 1757 1755 <&apps_smmu 0x596 0x0011>; 1758 1756 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1759 1757 interconnect-names = "memory"; 1758 + /* FIXME: dependency BAM DMA is disabled */ 1759 + status = "disabled"; 1760 1760 }; 1761 1761 1762 1762 ipa: ipa@1e40000 {
+8 -8
arch/arm64/boot/dts/rockchip/px30.dtsi
··· 291 291 }; 292 292 power-domain@PX30_PD_MMC_NAND { 293 293 reg = <PX30_PD_MMC_NAND>; 294 - clocks = <&cru HCLK_NANDC>, 295 - <&cru HCLK_EMMC>, 296 - <&cru HCLK_SDIO>, 297 - <&cru HCLK_SFC>, 298 - <&cru SCLK_EMMC>, 299 - <&cru SCLK_NANDC>, 300 - <&cru SCLK_SDIO>, 301 - <&cru SCLK_SFC>; 294 + clocks = <&cru HCLK_NANDC>, 295 + <&cru HCLK_EMMC>, 296 + <&cru HCLK_SDIO>, 297 + <&cru HCLK_SFC>, 298 + <&cru SCLK_EMMC>, 299 + <&cru SCLK_NANDC>, 300 + <&cru SCLK_SDIO>, 301 + <&cru SCLK_SFC>; 302 302 pm_qos = <&qos_emmc>, <&qos_nand>, 303 303 <&qos_sdio>, <&qos_sfc>; 304 304 #power-domain-cells = <0>;
-1
arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
··· 106 106 regulator-name = "vdd_core"; 107 107 regulator-min-microvolt = <827000>; 108 108 regulator-max-microvolt = <1340000>; 109 - regulator-init-microvolt = <1015000>; 110 109 regulator-settling-time-up-us = <250>; 111 110 regulator-always-on; 112 111 regulator-boot-on;
-1
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
··· 105 105 regulator-name = "vdd_core"; 106 106 regulator-min-microvolt = <827000>; 107 107 regulator-max-microvolt = <1340000>; 108 - regulator-init-microvolt = <1015000>; 109 108 regulator-settling-time-up-us = <250>; 110 109 regulator-always-on; 111 110 regulator-boot-on;
+1 -1
arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
··· 773 773 compatible = "brcm,bcm4329-fmac"; 774 774 reg = <1>; 775 775 interrupt-parent = <&gpio0>; 776 - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; 776 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; 777 777 interrupt-names = "host-wake"; 778 778 pinctrl-names = "default"; 779 779 pinctrl-0 = <&wifi_host_wake_l>;
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
··· 375 375 vcc_sdio: LDO_REG4 { 376 376 regulator-always-on; 377 377 regulator-boot-on; 378 - regulator-init-microvolt = <3000000>; 379 378 regulator-min-microvolt = <1800000>; 380 379 regulator-max-microvolt = <3300000>; 381 380 regulator-name = "vcc_sdio";
+1 -2
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
··· 548 548 &sdhci { 549 549 max-frequency = <150000000>; 550 550 bus-width = <8>; 551 - mmc-hs400-1_8v; 551 + mmc-hs200-1_8v; 552 552 non-removable; 553 - mmc-hs400-enhanced-strobe; 554 553 status = "okay"; 555 554 }; 556 555
+3 -3
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
··· 45 45 sdio_pwrseq: sdio-pwrseq { 46 46 compatible = "mmc-pwrseq-simple"; 47 47 clocks = <&rk808 1>; 48 - clock-names = "ext_clock"; 48 + clock-names = "lpo"; 49 49 pinctrl-names = "default"; 50 50 pinctrl-0 = <&wifi_enable_h>; 51 51 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ··· 645 645 }; 646 646 647 647 &sdhci { 648 + max-frequency = <150000000>; 648 649 bus-width = <8>; 649 - mmc-hs400-1_8v; 650 - mmc-hs400-enhanced-strobe; 650 + mmc-hs200-1_8v; 651 651 non-removable; 652 652 status = "okay"; 653 653 };
+1 -1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
··· 31 31 compatible = "brcm,bcm4329-fmac"; 32 32 reg = <1>; 33 33 interrupt-parent = <&gpio0>; 34 - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; 34 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; 35 35 interrupt-names = "host-wake"; 36 36 pinctrl-names = "default"; 37 37 pinctrl-0 = <&wifi_host_wake_l>;
-3
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
··· 356 356 regulator-boot-on; 357 357 regulator-min-microvolt = <500000>; 358 358 regulator-max-microvolt = <1350000>; 359 - regulator-init-microvolt = <900000>; 360 359 regulator-ramp-delay = <6001>; 361 360 regulator-initial-mode = <0x2>; 362 361 regulator-name = "vdd_logic"; ··· 370 371 regulator-boot-on; 371 372 regulator-min-microvolt = <500000>; 372 373 regulator-max-microvolt = <1350000>; 373 - regulator-init-microvolt = <900000>; 374 374 regulator-ramp-delay = <6001>; 375 375 regulator-initial-mode = <0x2>; 376 376 regulator-name = "vdd_gpu"; ··· 531 533 regulator-boot-on; 532 534 regulator-min-microvolt = <712500>; 533 535 regulator-max-microvolt = <1390000>; 534 - regulator-init-microvolt = <900000>; 535 536 regulator-name = "vdd_cpu"; 536 537 regulator-ramp-delay = <2300>; 537 538 vin-supply = <&vcc_sys>;
+2 -2
arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
··· 239 239 240 240 &gmac1 { 241 241 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 242 - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; 242 + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; 243 243 phy-mode = "rgmii"; 244 244 clock_in_out = "input"; 245 245 pinctrl-names = "default"; ··· 416 416 compatible = "brcm,bcm4329-fmac"; 417 417 reg = <1>; 418 418 interrupt-parent = <&gpio2>; 419 - interrupts = <RK_PB2 GPIO_ACTIVE_HIGH>; 419 + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>; 420 420 interrupt-names = "host-wake"; 421 421 pinctrl-names = "default"; 422 422 pinctrl-0 = <&wifi_host_wake_h>;
-3
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
··· 218 218 regulator-boot-on; 219 219 regulator-min-microvolt = <500000>; 220 220 regulator-max-microvolt = <1350000>; 221 - regulator-init-microvolt = <900000>; 222 221 regulator-ramp-delay = <6001>; 223 222 regulator-initial-mode = <0x2>; 224 223 ··· 232 233 regulator-boot-on; 233 234 regulator-min-microvolt = <500000>; 234 235 regulator-max-microvolt = <1350000>; 235 - regulator-init-microvolt = <900000>; 236 236 regulator-ramp-delay = <6001>; 237 237 regulator-initial-mode = <0x2>; 238 238 ··· 257 259 regulator-boot-on; 258 260 regulator-min-microvolt = <500000>; 259 261 regulator-max-microvolt = <1350000>; 260 - regulator-init-microvolt = <900000>; 261 262 regulator-ramp-delay = <6001>; 262 263 regulator-initial-mode = <0x2>; 263 264
-2
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
··· 264 264 regulator-always-on; 265 265 regulator-min-microvolt = <500000>; 266 266 regulator-max-microvolt = <1350000>; 267 - regulator-init-microvolt = <900000>; 268 267 regulator-ramp-delay = <6001>; 269 268 regulator-initial-mode = <0x2>; 270 269 ··· 277 278 regulator-name = "vdd_gpu_npu"; 278 279 regulator-min-microvolt = <500000>; 279 280 regulator-max-microvolt = <1350000>; 280 - regulator-init-microvolt = <900000>; 281 281 regulator-ramp-delay = <6001>; 282 282 regulator-initial-mode = <0x2>; 283 283
-2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
··· 366 366 regulator-boot-on; 367 367 regulator-min-microvolt = <500000>; 368 368 regulator-max-microvolt = <1350000>; 369 - regulator-init-microvolt = <900000>; 370 369 regulator-ramp-delay = <6001>; 371 370 regulator-initial-mode = <0x2>; 372 371 regulator-name = "vdd_logic"; ··· 380 381 regulator-boot-on; 381 382 regulator-min-microvolt = <500000>; 382 383 regulator-max-microvolt = <1350000>; 383 - regulator-init-microvolt = <900000>; 384 384 regulator-ramp-delay = <6001>; 385 385 regulator-initial-mode = <0x2>; 386 386 regulator-name = "vdd_gpu";
-2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
··· 277 277 regulator-boot-on; 278 278 regulator-min-microvolt = <500000>; 279 279 regulator-max-microvolt = <1350000>; 280 - regulator-init-microvolt = <900000>; 281 280 regulator-ramp-delay = <6001>; 282 281 283 282 regulator-state-mem { ··· 291 292 regulator-boot-on; 292 293 regulator-min-microvolt = <900000>; 293 294 regulator-max-microvolt = <1350000>; 294 - regulator-init-microvolt = <900000>; 295 295 regulator-ramp-delay = <6001>; 296 296 297 297 regulator-state-mem {
+2 -2
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
··· 137 137 138 138 &mdio1 { 139 139 rgmii_phy1: ethernet-phy@0 { 140 - compatible="ethernet-phy-ieee802.3-c22"; 141 - reg= <0x0>; 140 + compatible = "ethernet-phy-ieee802.3-c22"; 141 + reg = <0x0>; 142 142 }; 143 143 }; 144 144
-2
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
··· 278 278 regulator-boot-on; 279 279 regulator-min-microvolt = <500000>; 280 280 regulator-max-microvolt = <1350000>; 281 - regulator-init-microvolt = <900000>; 282 281 regulator-ramp-delay = <6001>; 283 282 284 283 regulator-state-mem { ··· 290 291 regulator-name = "vdd_gpu"; 291 292 regulator-min-microvolt = <900000>; 292 293 regulator-max-microvolt = <1350000>; 293 - regulator-init-microvolt = <900000>; 294 294 regulator-ramp-delay = <6001>; 295 295 296 296 regulator-state-mem {
-3
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
··· 234 234 regulator-boot-on; 235 235 regulator-min-microvolt = <500000>; 236 236 regulator-max-microvolt = <1350000>; 237 - regulator-init-microvolt = <900000>; 238 237 regulator-ramp-delay = <6001>; 239 238 regulator-initial-mode = <0x2>; 240 239 regulator-state-mem { ··· 248 249 regulator-boot-on; 249 250 regulator-min-microvolt = <500000>; 250 251 regulator-max-microvolt = <1350000>; 251 - regulator-init-microvolt = <900000>; 252 252 regulator-ramp-delay = <6001>; 253 253 regulator-initial-mode = <0x2>; 254 254 regulator-state-mem { ··· 270 272 regulator-boot-on; 271 273 regulator-min-microvolt = <500000>; 272 274 regulator-max-microvolt = <1350000>; 273 - regulator-init-microvolt = <900000>; 274 275 regulator-initial-mode = <0x2>; 275 276 regulator-name = "vdd_npu"; 276 277 regulator-state-mem {
-3
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
··· 308 308 regulator-name = "vdd_logic"; 309 309 regulator-always-on; 310 310 regulator-boot-on; 311 - regulator-init-microvolt = <900000>; 312 311 regulator-initial-mode = <0x2>; 313 312 regulator-min-microvolt = <500000>; 314 313 regulator-max-microvolt = <1350000>; ··· 321 322 vdd_gpu: DCDC_REG2 { 322 323 regulator-name = "vdd_gpu"; 323 324 regulator-always-on; 324 - regulator-init-microvolt = <900000>; 325 325 regulator-initial-mode = <0x2>; 326 326 regulator-min-microvolt = <500000>; 327 327 regulator-max-microvolt = <1350000>; ··· 344 346 345 347 vdd_npu: DCDC_REG4 { 346 348 regulator-name = "vdd_npu"; 347 - regulator-init-microvolt = <900000>; 348 349 regulator-initial-mode = <0x2>; 349 350 regulator-min-microvolt = <500000>; 350 351 regulator-max-microvolt = <1350000>;
-3
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
··· 293 293 regulator-name = "vdd_logic"; 294 294 regulator-always-on; 295 295 regulator-boot-on; 296 - regulator-init-microvolt = <900000>; 297 296 regulator-initial-mode = <0x2>; 298 297 regulator-min-microvolt = <500000>; 299 298 regulator-max-microvolt = <1350000>; ··· 306 307 vdd_gpu: DCDC_REG2 { 307 308 regulator-name = "vdd_gpu"; 308 309 regulator-always-on; 309 - regulator-init-microvolt = <900000>; 310 310 regulator-initial-mode = <0x2>; 311 311 regulator-min-microvolt = <500000>; 312 312 regulator-max-microvolt = <1350000>; ··· 329 331 330 332 vdd_npu: DCDC_REG4 { 331 333 regulator-name = "vdd_npu"; 332 - regulator-init-microvolt = <900000>; 333 334 regulator-initial-mode = <0x2>; 334 335 regulator-min-microvolt = <500000>; 335 336 regulator-max-microvolt = <1350000>;
-4
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
··· 173 173 regulator-name = "vdd_logic"; 174 174 regulator-always-on; 175 175 regulator-boot-on; 176 - regulator-init-microvolt = <900000>; 177 176 regulator-initial-mode = <0x2>; 178 177 regulator-min-microvolt = <500000>; 179 178 regulator-max-microvolt = <1350000>; ··· 186 187 vdd_gpu: DCDC_REG2 { 187 188 regulator-name = "vdd_gpu"; 188 189 regulator-always-on; 189 - regulator-init-microvolt = <900000>; 190 190 regulator-initial-mode = <0x2>; 191 191 regulator-min-microvolt = <500000>; 192 192 regulator-max-microvolt = <1350000>; ··· 209 211 210 212 vdd_npu: DCDC_REG4 { 211 213 regulator-name = "vdd_npu"; 212 - regulator-init-microvolt = <900000>; 213 214 regulator-initial-mode = <0x2>; 214 215 regulator-min-microvolt = <500000>; 215 216 regulator-max-microvolt = <1350000>; ··· 327 330 328 331 vcca1v8_image: LDO_REG9 { 329 332 regulator-name = "vcca1v8_image"; 330 - regulator-init-microvolt = <950000>; 331 333 regulator-min-microvolt = <950000>; 332 334 regulator-max-microvolt = <1800000>; 333 335
-3
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
··· 243 243 regulator-boot-on; 244 244 regulator-min-microvolt = <500000>; 245 245 regulator-max-microvolt = <1350000>; 246 - regulator-init-microvolt = <900000>; 247 246 regulator-ramp-delay = <6001>; 248 247 regulator-initial-mode = <0x2>; 249 248 ··· 257 258 regulator-boot-on; 258 259 regulator-min-microvolt = <500000>; 259 260 regulator-max-microvolt = <1350000>; 260 - regulator-init-microvolt = <900000>; 261 261 regulator-ramp-delay = <6001>; 262 262 regulator-initial-mode = <0x2>; 263 263 ··· 282 284 regulator-boot-on; 283 285 regulator-min-microvolt = <500000>; 284 286 regulator-max-microvolt = <1350000>; 285 - regulator-init-microvolt = <900000>; 286 287 regulator-ramp-delay = <6001>; 287 288 regulator-initial-mode = <0x2>; 288 289
-3
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
··· 232 232 regulator-name = "vdd_logic"; 233 233 regulator-always-on; 234 234 regulator-boot-on; 235 - regulator-init-microvolt = <900000>; 236 235 regulator-initial-mode = <0x2>; 237 236 regulator-min-microvolt = <500000>; 238 237 regulator-max-microvolt = <1350000>; ··· 245 246 vdd_gpu: DCDC_REG2 { 246 247 regulator-name = "vdd_gpu"; 247 248 regulator-always-on; 248 - regulator-init-microvolt = <900000>; 249 249 regulator-initial-mode = <0x2>; 250 250 regulator-min-microvolt = <500000>; 251 251 regulator-max-microvolt = <1350000>; ··· 268 270 269 271 vdd_npu: DCDC_REG4 { 270 272 regulator-name = "vdd_npu"; 271 - regulator-init-microvolt = <900000>; 272 273 regulator-initial-mode = <0x2>; 273 274 regulator-min-microvolt = <500000>; 274 275 regulator-max-microvolt = <1350000>;
-3
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
··· 291 291 regulator-name = "vdd_logic"; 292 292 regulator-always-on; 293 293 regulator-boot-on; 294 - regulator-init-microvolt = <900000>; 295 294 regulator-initial-mode = <0x2>; 296 295 regulator-min-microvolt = <500000>; 297 296 regulator-max-microvolt = <1350000>; ··· 304 305 vdd_gpu: DCDC_REG2 { 305 306 regulator-name = "vdd_gpu"; 306 307 regulator-always-on; 307 - regulator-init-microvolt = <900000>; 308 308 regulator-initial-mode = <0x2>; 309 309 regulator-min-microvolt = <500000>; 310 310 regulator-max-microvolt = <1350000>; ··· 327 329 328 330 vdd_npu: DCDC_REG4 { 329 331 regulator-name = "vdd_npu"; 330 - regulator-init-microvolt = <900000>; 331 332 regulator-initial-mode = <0x2>; 332 333 regulator-min-microvolt = <500000>; 333 334 regulator-max-microvolt = <1350000>;
-3
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
··· 163 163 regulator-name = "vdd_logic"; 164 164 regulator-always-on; 165 165 regulator-boot-on; 166 - regulator-init-microvolt = <900000>; 167 166 regulator-initial-mode = <0x2>; 168 167 regulator-min-microvolt = <500000>; 169 168 regulator-max-microvolt = <1350000>; ··· 176 177 vdd_gpu: DCDC_REG2 { 177 178 regulator-name = "vdd_gpu"; 178 179 regulator-always-on; 179 - regulator-init-microvolt = <900000>; 180 180 regulator-initial-mode = <0x2>; 181 181 regulator-min-microvolt = <500000>; 182 182 regulator-max-microvolt = <1350000>; ··· 199 201 200 202 vdd_npu: DCDC_REG4 { 201 203 regulator-name = "vdd_npu"; 202 - regulator-init-microvolt = <900000>; 203 204 regulator-initial-mode = <0x2>; 204 205 regulator-min-microvolt = <500000>; 205 206 regulator-max-microvolt = <1350000>;
-3
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
··· 350 350 regulator-name = "vdd_logic"; 351 351 regulator-always-on; 352 352 regulator-boot-on; 353 - regulator-init-microvolt = <900000>; 354 353 regulator-initial-mode = <0x2>; 355 354 regulator-min-microvolt = <500000>; 356 355 regulator-max-microvolt = <1350000>; ··· 363 364 vdd_gpu: DCDC_REG2 { 364 365 regulator-name = "vdd_gpu"; 365 366 regulator-always-on; 366 - regulator-init-microvolt = <900000>; 367 367 regulator-initial-mode = <0x2>; 368 368 regulator-min-microvolt = <500000>; 369 369 regulator-max-microvolt = <1350000>; ··· 386 388 387 389 vdd_npu: DCDC_REG4 { 388 390 regulator-name = "vdd_npu"; 389 - regulator-init-microvolt = <900000>; 390 391 regulator-initial-mode = <0x2>; 391 392 regulator-min-microvolt = <500000>; 392 393 regulator-max-microvolt = <1350000>;
-1
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
··· 337 337 regulator-boot-on; 338 338 regulator-min-microvolt = <550000>; 339 339 regulator-max-microvolt = <950000>; 340 - regulator-init-microvolt = <750000>; 341 340 regulator-ramp-delay = <12500>; 342 341 regulator-name = "vdd_vdenc_s0"; 343 342
+4 -4
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
··· 125 125 cpu-supply = <&vdd_cpu_lit_s0>; 126 126 }; 127 127 128 - &cpu_b0{ 128 + &cpu_b0 { 129 129 cpu-supply = <&vdd_cpu_big0_s0>; 130 130 }; 131 131 132 - &cpu_b1{ 132 + &cpu_b1 { 133 133 cpu-supply = <&vdd_cpu_big0_s0>; 134 134 }; 135 135 136 - &cpu_b2{ 136 + &cpu_b2 { 137 137 cpu-supply = <&vdd_cpu_big1_s0>; 138 138 }; 139 139 140 - &cpu_b3{ 140 + &cpu_b3 { 141 141 cpu-supply = <&vdd_cpu_big1_s0>; 142 142 }; 143 143
+2
drivers/bus/ti-sysc.c
··· 2142 2142 sysc_val = sysc_read_sysconfig(ddata); 2143 2143 sysc_val |= sysc_mask; 2144 2144 sysc_write(ddata, sysc_offset, sysc_val); 2145 + /* Flush posted write */ 2146 + sysc_val = sysc_read_sysconfig(ddata); 2145 2147 } 2146 2148 2147 2149 if (ddata->cfg.srst_udelay)
+1
drivers/soc/aspeed/aspeed-socinfo.c
··· 137 137 138 138 soc_dev = soc_device_register(attrs); 139 139 if (IS_ERR(soc_dev)) { 140 + kfree(attrs->machine); 140 141 kfree(attrs->soc_id); 141 142 kfree(attrs->serial_number); 142 143 kfree(attrs);
+1 -1
drivers/soc/aspeed/aspeed-uart-routing.c
··· 524 524 struct aspeed_uart_routing_selector *sel = to_routing_selector(attr); 525 525 int val; 526 526 527 - val = match_string(sel->options, -1, buf); 527 + val = __sysfs_match_string(sel->options, -1, buf); 528 528 if (val < 0) { 529 529 dev_err(dev, "invalid value \"%s\"\n", buf); 530 530 return -EINVAL;