tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks

Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd f235f6ae 1775790e

+93 -92
+6 -6
drivers/clk/mediatek/clk-mt6765.c
··· 406 406 CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31, 407 407 CLK_CFG_UPDATE, 11), 408 408 /* CLK_CFG_3 */ 409 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk", 409 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk", 410 410 msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET, 411 - CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12), 412 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 411 + CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0), 412 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 413 413 msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET, 414 - CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13), 415 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 414 + CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0), 415 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 416 416 msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET, 417 - CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14), 417 + CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0), 418 418 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 419 419 CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 420 420 24, 2, 31, CLK_CFG_UPDATE, 15),
+9 -9
drivers/clk/mediatek/clk-mt6779.c
··· 687 687 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20), 688 688 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents, 689 689 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21), 690 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", 691 - msdc50_hclk_parents, 0x70, 0x74, 0x78, 692 - 16, 2, 23, 0x004, 22), 693 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel", 694 - msdc50_0_parents, 0x70, 0x74, 0x78, 695 - 24, 3, 31, 0x004, 23), 690 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", 691 + msdc50_hclk_parents, 0x70, 0x74, 0x78, 692 + 16, 2, 23, 0x004, 22, 0), 693 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel", 694 + msdc50_0_parents, 0x70, 0x74, 0x78, 695 + 24, 3, 31, 0x004, 23, 0), 696 696 /* CLK_CFG_6 */ 697 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel", 698 - msdc30_1_parents, 0x80, 0x84, 0x88, 699 - 0, 3, 7, 0x004, 24), 697 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel", 698 + msdc30_1_parents, 0x80, 0x84, 0x88, 699 + 0, 3, 7, 0x004, 24, 0), 700 700 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents, 701 701 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25), 702 702 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
+6 -6
drivers/clk/mediatek/clk-mt7981-topckgen.c
··· 310 310 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 311 311 0x1C0, 7), 312 312 /* CLK_CFG_2 */ 313 - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", 314 - emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 315 - 0x1C0, 8), 316 - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", 317 - emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 318 - 0x1C0, 9), 313 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", 314 + emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 315 + 0x1C0, 8, 0), 316 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", 317 + emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 318 + 0x1C0, 9, 0), 319 319 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 320 320 csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, 321 321 0x1C0, 10,
+6 -6
drivers/clk/mediatek/clk-mt7986-topckgen.c
··· 193 193 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 194 194 31, 0x1C0, 7), 195 195 /* CLK_CFG_2 */ 196 - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", 197 - emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 198 - 0x1C0, 8), 199 - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", 200 - emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 201 - 0x1C0, 9), 196 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", 197 + emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 198 + 0x1C0, 8, 0), 199 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", 200 + emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 201 + 0x1C0, 9, 0), 202 202 MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", 203 203 f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 204 204 0x1C0, 10),
+12 -12
drivers/clk/mediatek/clk-mt8173-topckgen.c
··· 547 547 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31), 548 548 /* CLK_CFG_3 */ 549 549 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7), 550 - MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 551 - 0x0070, 8, 3, 15), 552 - MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 553 - 0x0070, 16, 4, 23), 554 - MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 555 - 0x0070, 24, 3, 31), 550 + MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 551 + 0x0070, 8, 3, 15, 0), 552 + MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 553 + 0x0070, 16, 4, 23, 0), 554 + MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 555 + 0x0070, 24, 3, 31, 0), 556 556 /* CLK_CFG_4 */ 557 - MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 558 - 0x0080, 0, 3, 7), 559 - MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 560 - 0x0080, 8, 4, 15), 557 + MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 558 + 0x0080, 0, 3, 7, 0), 559 + MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 560 + 0x0080, 8, 4, 15, 0), 561 561 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 562 562 0x0080, 16, 2, 23), 563 563 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, ··· 595 595 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 596 596 0x00c0, 24, 3, 31), 597 597 /* CLK_CFG_13 */ 598 - MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 599 - 0x00d0, 0, 3, 7), 598 + MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 599 + 0x00d0, 0, 3, 7, 0), 600 600 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), 601 601 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 602 602 0x00d0, 16, 2, 23),
+8 -8
drivers/clk/mediatek/clk-mt8183.c
··· 487 487 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 488 488 spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), 489 489 /* CLK_CFG_4 */ 490 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 491 - msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16), 492 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 493 - msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17), 494 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 495 - msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18), 496 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 497 - msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19), 490 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 491 + msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0), 492 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 493 + msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0), 494 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 495 + msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0), 496 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 497 + msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0), 498 498 /* CLK_CFG_5 */ 499 499 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 500 500 audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20),
+6 -6
drivers/clk/mediatek/clk-mt8186-topckgen.c
··· 531 531 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi", 532 532 spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11), 533 533 /* CLK_CFG_3 */ 534 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk", 535 - msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12), 536 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0", 537 - msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13), 538 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1", 539 - msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14), 534 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk", 535 + msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12, 0), 536 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0", 537 + msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13, 0), 538 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1", 539 + msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14, 0), 540 540 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio", 541 541 audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15), 542 542 /* CLK_CFG_4 */
+8 -8
drivers/clk/mediatek/clk-mt8188-topckgen.c
··· 1015 1015 uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24), 1016 1016 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi", 1017 1017 spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25), 1018 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk", 1019 - msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26), 1020 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0", 1021 - msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27), 1018 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk", 1019 + msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0), 1020 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0", 1021 + msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0), 1022 1022 /* CLK_CFG_7 */ 1023 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1", 1024 - msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28), 1025 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2", 1026 - msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29), 1023 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1", 1024 + msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0), 1025 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2", 1026 + msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0), 1027 1027 MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir", 1028 1028 intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30), 1029 1029 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
+9 -8
drivers/clk/mediatek/clk-mt8192.c
··· 601 601 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 602 602 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 603 603 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 604 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 605 - msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), 604 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 605 + msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 606 + 31, 0x004, 27, 0), 606 607 /* CLK_CFG_7 */ 607 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 608 - msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), 609 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 610 - msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), 611 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 612 - msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), 608 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 609 + msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0), 610 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 611 + msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0), 612 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 613 + msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0), 613 614 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 614 615 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 615 616 /* CLK_CFG_8 */
+8 -8
drivers/clk/mediatek/clk-mt8195-topckgen.c
··· 930 930 /* CLK_CFG_7 */ 931 931 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis", 932 932 spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28), 933 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk", 934 - msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29), 935 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0", 936 - msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30), 937 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1", 938 - msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31), 933 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk", 934 + msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0), 935 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0", 936 + msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0), 937 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1", 938 + msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0), 939 939 /* CLK_CFG_8 */ 940 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2", 941 - msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0), 940 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2", 941 + msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0), 942 942 MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir", 943 943 intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1), 944 944 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
+15 -15
drivers/clk/mediatek/clk-mt8365.c
··· 431 431 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 432 432 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 433 433 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 434 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 435 - msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 436 - 23, CLK_CFG_UPDATE, 10), 437 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 438 - msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 439 - 31, CLK_CFG_UPDATE, 11), 434 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 435 + msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 436 + 23, CLK_CFG_UPDATE, 10, 0), 437 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 438 + msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 439 + 31, CLK_CFG_UPDATE, 11, 0), 440 440 /* CLK_CFG_3 */ 441 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 442 - msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 443 - CLK_CFG_UPDATE, 12), 444 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 445 - msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 446 - CLK_CFG_UPDATE, 13), 447 - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 448 - msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 449 - CLK_CFG_UPDATE, 14), 441 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 442 + msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 443 + CLK_CFG_UPDATE, 12, 0), 444 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 445 + msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 446 + CLK_CFG_UPDATE, 13, 0), 447 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 448 + msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 449 + CLK_CFG_UPDATE, 14, 0), 450 450 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 451 451 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 452 452 15),