tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag

The clk-mux driver was forcing the CLK_SET_RATE_PARENT flag even for
the GATE_CLK_SET_UPD_FLAGS() macro, as in mtk_clk_register_mux() the
flag was unconditionally added.

In preparation for a change on MSDC clock muxes, stop forcing this
flag and, where necessary, update clock drivers to add it so that
with this commit we introduce no functional changes for the currently
supported SoCs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-2-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd 1775790e 5f17cdb0

+62 -40
+5 -3
drivers/clk/mediatek/clk-mt6765.c
··· 367 367 /* CLK_CFG_0 */ 368 368 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 369 369 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 370 - 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), 370 + 0, 2, 7, CLK_CFG_UPDATE, 0, 371 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 371 372 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 372 373 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 373 - 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), 374 + 8, 2, 15, CLK_CFG_UPDATE, 1, 375 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 374 376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, 375 377 CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, 376 378 CLK_CFG_UPDATE, 2), ··· 461 459 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel", 462 460 ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET, 463 461 CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28, 464 - CLK_IS_CRITICAL), 462 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 465 463 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents, 466 464 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, 467 465 CLK_CFG_UPDATE, 29),
+3 -3
drivers/clk/mediatek/clk-mt6779.c
··· 640 640 /* CLK_CFG_0 */ 641 641 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents, 642 642 0x20, 0x24, 0x28, 0, 2, 7, 643 - 0x004, 0, CLK_IS_CRITICAL), 643 + 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 644 644 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents, 645 645 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1), 646 646 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents, ··· 710 710 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28), 711 711 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents, 712 712 0x90, 0x94, 0x98, 8, 3, 15, 713 - 0x004, 29, CLK_IS_CRITICAL), 713 + 0x004, 29, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 714 714 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents, 715 715 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30), 716 716 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents, ··· 727 727 16, 2, 23, 0x008, 3), 728 728 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents, 729 729 0xa0, 0xa4, 0xa8, 24, 2, 31, 730 - 0x008, 4, CLK_IS_CRITICAL), 730 + 0x008, 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 731 731 /* CLK_CFG_9 */ 732 732 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents, 733 733 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
+4 -2
drivers/clk/mediatek/clk-mt8183.c
··· 451 451 static const struct mtk_mux top_muxes[] = { 452 452 /* CLK_CFG_0 */ 453 453 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 454 - axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 454 + axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, 455 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 455 456 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 456 457 mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), 457 458 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", ··· 519 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 520 519 ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 521 520 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 522 - spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 521 + spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, 522 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 523 523 /* CLK_CFG_8 */ 524 524 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 525 525 i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
+6 -6
drivers/clk/mediatek/clk-mt8186-topckgen.c
··· 504 504 */ 505 505 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents, 506 506 0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0, 507 - CLK_IS_CRITICAL), 507 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 508 508 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents, 509 509 0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1, 510 - CLK_IS_CRITICAL), 510 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 511 511 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg", 512 512 mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2), 513 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg", ··· 559 559 disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21), 560 560 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents, 561 561 0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22, 562 - CLK_IS_CRITICAL), 562 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 563 563 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc", 564 564 dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23), 565 565 /* ··· 570 570 usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24), 571 571 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents, 572 572 0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25, 573 - CLK_IS_CRITICAL), 573 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 574 574 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents, 575 575 0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26, 576 - CLK_IS_CRITICAL), 576 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 577 577 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c", 578 578 i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27), 579 579 /* CLK_CFG_7 */ ··· 627 627 */ 628 628 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents, 629 629 0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17, 630 - CLK_IS_CRITICAL), 630 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 631 631 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ", 632 632 dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18), 633 633 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
+16 -8
drivers/clk/mediatek/clk-mt8188-topckgen.c
··· 954 954 * spm_sel and scp_sel are main clocks in always-on co-processor. 955 955 */ 956 956 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents, 957 - 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, CLK_IS_CRITICAL), 957 + 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, 958 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 958 959 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents, 959 - 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, CLK_IS_CRITICAL), 960 + 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, 961 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 960 962 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents, 961 - 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, CLK_IS_CRITICAL), 963 + 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, 964 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 962 965 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents, 963 - 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, CLK_IS_CRITICAL), 966 + 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, 967 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 964 968 /* CLK_CFG_1 */ 965 969 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp", 966 970 vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4), ··· 1082 1078 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm", 1083 1079 pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21), 1084 1080 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents, 1085 - 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, CLK_IS_CRITICAL), 1081 + 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, 1082 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1086 1083 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst", 1087 1084 spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23), 1088 1085 /* ··· 1093 1088 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst", 1094 1089 spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24), 1095 1090 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents, 1096 - 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, CLK_IS_CRITICAL), 1091 + 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, 1092 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1097 1093 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl", 1098 1094 tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26), 1099 1095 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde", ··· 1170 1164 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor", 1171 1165 spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24), 1172 1166 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents, 1173 - 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, CLK_IS_CRITICAL), 1167 + 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, 1168 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1174 1169 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents, 1175 - 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, CLK_IS_CRITICAL), 1170 + 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, 1171 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1176 1172 }; 1177 1173 1178 1174 static const struct mtk_composite top_adj_divs[] = {
+3 -3
drivers/clk/mediatek/clk-mt8192.c
··· 549 549 /* CLK_CFG_0 */ 550 550 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 551 551 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 552 - CLK_IS_CRITICAL), 552 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 553 553 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 554 554 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 555 - CLK_IS_CRITICAL), 555 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 556 556 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 557 557 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 558 558 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 559 559 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 560 - CLK_IS_CRITICAL), 560 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 561 561 /* CLK_CFG_1 */ 562 562 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 563 563 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
+20 -10
drivers/clk/mediatek/clk-mt8195-topckgen.c
··· 862 862 * top_spm and top_scp are main clocks in always-on co-processor. 863 863 */ 864 864 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", 865 - axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL), 865 + axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, 866 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 866 867 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", 867 - spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL), 868 + spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, 869 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 868 870 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", 869 - scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL), 871 + scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, 872 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 870 873 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", 871 - bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL), 874 + bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, 875 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 872 876 /* CLK_CFG_1 */ 873 877 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp", 874 878 vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4), ··· 955 951 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb", 956 952 atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5), 957 953 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu", 958 - pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL), 954 + pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, 955 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 959 956 MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", 960 957 dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), 961 958 /* CLK_CFG_10 */ ··· 1025 1020 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm", 1026 1021 pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2), 1027 1022 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", 1028 - mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL), 1023 + mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, 1024 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1029 1025 /* 1030 1026 * CLK_CFG_17 1031 1027 * top_dvfsrc is for internal DVFS usage, should not be handled by Linux. ··· 1036 1030 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst", 1037 1031 spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5), 1038 1032 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", 1039 - dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL), 1033 + dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, 1034 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1040 1035 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl", 1041 1036 tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7), 1042 1037 /* CLK_CFG_18 */ ··· 1148 1141 MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref", 1149 1142 dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20), 1150 1143 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", 1151 - ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL), 1144 + ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, 1145 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1152 1146 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core", 1153 - ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL), 1147 + ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, 1148 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1154 1149 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", 1155 - srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL), 1150 + srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, 1151 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 1156 1152 /* 1157 1153 * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled 1158 1154 * by Linux.
+4 -4
drivers/clk/mediatek/clk-mt8365.c
··· 410 410 /* CLK_CFG_0 */ 411 411 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 412 412 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 413 - 0, CLK_IS_CRITICAL), 413 + 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 414 414 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 415 415 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 416 416 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, ··· 475 475 /* CLK_CFG_6 */ 476 476 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 477 477 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 478 - 24, CLK_IS_CRITICAL), 478 + 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 479 479 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 480 480 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 481 481 CLK_CFG_UPDATE, 25), ··· 483 483 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 484 484 CLK_CFG_UPDATE, 26), 485 485 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 486 - 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, 487 - CLK_CFG_UPDATE, 27, CLK_IS_CRITICAL), 486 + 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE, 487 + 27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 488 488 /* CLK_CFG_7 */ 489 489 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 490 490 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
+1 -1
drivers/clk/mediatek/clk-mux.c
··· 168 168 return ERR_PTR(-ENOMEM); 169 169 170 170 init.name = mux->name; 171 - init.flags = mux->flags | CLK_SET_RATE_PARENT; 171 + init.flags = mux->flags; 172 172 init.parent_names = mux->parent_names; 173 173 init.num_parents = mux->num_parents; 174 174 init.ops = mux->ops;