ath9k: Remove a few unused macros and fix indentation

Signed-off-by: Sujith Manoharan <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

authored by Sujith and committed by John W. Linville f22f558d 06df8bea

+130 -145
+130 -145
drivers/net/wireless/ath9k/core.h
··· 51 52 /* Macro to expand scalars to 64-bit objects */ 53 54 - #define ito64(x) (sizeof(x) == 8) ? \ 55 - (((unsigned long long int)(x)) & (0xff)) : \ 56 - (sizeof(x) == 16) ? \ 57 - (((unsigned long long int)(x)) & 0xffff) : \ 58 - ((sizeof(x) == 32) ? \ 59 (((unsigned long long int)(x)) & 0xffffffff) : \ 60 - (unsigned long long int)(x)) 61 62 /* increment with wrap-around */ 63 - #define INCR(_l, _sz) do { \ 64 - (_l)++; \ 65 - (_l) &= ((_sz) - 1); \ 66 } while (0) 67 68 /* decrement with wrap-around */ 69 - #define DECR(_l, _sz) do { \ 70 - (_l)--; \ 71 - (_l) &= ((_sz) - 1); \ 72 } while (0) 73 74 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) ··· 136 /* Per-instance load-time (note: NOT run-time) configurations 137 * for Atheros Device */ 138 struct ath_config { 139 - u32 ath_aggr_prot; 140 - u16 txpowlimit; 141 - u16 txpowlimit_override; 142 - u8 cabqReadytime; /* Cabq Readytime % */ 143 - u8 swBeaconProcess; /* Process received beacons 144 - in SW (vs HW) */ 145 }; 146 147 /***********************/ ··· 160 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35 161 /* Struct to store the chainmask select related info */ 162 struct ath_chainmask_sel { 163 - struct timer_list timer; 164 - int cur_tx_mask; /* user configured or 3x3 */ 165 - int cur_rx_mask; /* user configured or 3x3 */ 166 - int tx_avgrssi; 167 - u8 switch_allowed:1, /* timer will set this */ 168 - cm_sel_enabled:1; 169 }; 170 171 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an); ··· 191 192 struct ath_buf_state { 193 int bfs_nframes; /* # frames in aggregate */ 194 - u16 bfs_al; /* length of aggregate */ 195 - u16 bfs_frmlen; /* length of frame */ 196 int bfs_seqno; /* sequence number */ 197 int bfs_tidno; /* tid of this frame */ 198 int bfs_retries; /* current retries */ ··· 204 u8 bfs_isretried:1; /* is retried */ 205 u8 bfs_isxretried:1; /* is excessive retried */ 206 u8 bfs_shpreamble:1; /* is short preamble */ 207 - u8 bfs_isbar:1; /* is a BAR */ 208 u8 bfs_ispspoll:1; /* is a PS-Poll */ 209 u8 bfs_aggrburst:1; /* is a aggr burst */ 210 u8 bfs_calcairtime:1; /* requests airtime be calculated ··· 246 struct list_head list; 247 struct list_head *last; 248 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 249 - an aggregate) */ 250 struct ath_buf *bf_lastfrm; /* last buf of this frame */ 251 struct ath_buf *bf_next; /* next subframe in the aggregate */ 252 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */ ··· 256 dma_addr_t bf_daddr; /* physical addr of desc */ 257 dma_addr_t bf_buf_addr; /* physical addr of data buffer */ 258 u32 bf_status; 259 - u16 bf_flags; /* tx descriptor flags */ 260 struct ath_buf_state bf_state; /* buffer state */ 261 dma_addr_t bf_dmacontext; 262 }; ··· 330 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 331 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 332 int8_t abs_rssi; /* absolute RSSI */ 333 - u8 rateieee; /* data rate received (IEEE rate code) */ 334 - u8 ratecode; /* phy rate code */ 335 int rateKbps; /* data rate received (Kbps) */ 336 int antenna; /* rx antenna */ 337 int flags; /* status of associated skb */ ··· 350 }; 351 352 struct ath_rxbuf { 353 - struct sk_buff *rx_wbuf; /* buffer */ 354 - unsigned long rx_time; /* system time when received */ 355 - struct ath_recv_status rx_status; /* cached rx status */ 356 }; 357 358 /* Per-TID aggregate receiver state for a node */ 359 struct ath_arx_tid { 360 - struct ath_node *an; /* parent ath node */ 361 - struct ath_rxbuf *rxbuf; /* re-ordering buffer */ 362 - struct timer_list timer; 363 - spinlock_t tidlock; /* lock to protect this TID structure */ 364 - int baw_head; /* seq_next at head */ 365 - int baw_tail; /* tail of block-ack window */ 366 - int seq_reset; /* need to reset start sequence */ 367 - int addba_exchangecomplete; 368 - u16 seq_next; /* next expected sequence */ 369 - u16 baw_size; /* block-ack window size */ 370 }; 371 372 /* Per-node receiver aggregate state */ 373 struct ath_arx { 374 - struct ath_arx_tid tid[WME_NUM_TID]; 375 }; 376 377 int ath_startrecv(struct ath_softc *sc); ··· 443 * hardware queue). 444 */ 445 struct ath_txq { 446 - u32 axq_qnum; /* hardware q number */ 447 - u32 *axq_link; /* link ptr in last TX desc */ 448 - struct list_head axq_q; /* transmit queue */ 449 - spinlock_t axq_lock; /* lock on q and link */ 450 - unsigned long axq_lockflags; /* intr state when must cli */ 451 - u32 axq_depth; /* queue depth */ 452 - u8 axq_aggr_depth; /* aggregates queued */ 453 - u32 axq_totalqueued;/* total ever queued */ 454 - u32 axq_intrcnt; /* count to determine 455 - if descriptor should generate 456 - int on this txq. */ 457 - bool stopped; /* Is mac80211 queue 458 - stopped ? */ 459 - /* State for patching up CTS when bursting */ 460 - struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ 461 - struct ath_desc *axq_lastdsWithCTS; /* first desc of the 462 - last descriptor that contains CTS */ 463 - struct ath_desc *axq_gatingds; /* final desc of the gating desc 464 - * that determines whether lastdsWithCTS has 465 - * been DMA'ed or not */ 466 - struct list_head axq_acq; 467 }; 468 469 /* per TID aggregate tx state for a destination */ 470 struct ath_atx_tid { 471 - struct list_head list; /* round-robin tid entry */ 472 - struct list_head buf_q; /* pending buffers */ 473 - struct ath_node *an; /* parent node structure */ 474 - struct ath_atx_ac *ac; /* parent access category */ 475 - struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */ 476 - u16 seq_start; /* starting seq of BA window */ 477 - u16 seq_next; /* next seq to be used */ 478 - u16 baw_size; /* BA window size */ 479 - int tidno; /* TID number */ 480 - int baw_head; /* first un-acked tx buffer */ 481 - int baw_tail; /* next unused tx buffer slot */ 482 - int sched; /* TID is scheduled */ 483 - int paused; /* TID is paused */ 484 - int cleanup_inprogress; /* aggr of this TID is 485 - being teared down */ 486 - u32 addba_exchangecomplete:1; /* ADDBA state */ 487 - int32_t addba_exchangeinprogress; 488 - int addba_exchangeattempts; 489 }; 490 491 /* per access-category aggregate tx state for a destination */ 492 struct ath_atx_ac { 493 - int sched; /* dest-ac is scheduled */ 494 - int qnum; /* H/W queue number associated 495 - with this AC */ 496 - struct list_head list; /* round-robin txq entry */ 497 - struct list_head tid_q; /* queue of TIDs with buffers */ 498 }; 499 500 /* per dest tx state */ 501 struct ath_atx { 502 - struct ath_atx_tid tid[WME_NUM_TID]; 503 - struct ath_atx_ac ac[WME_NUM_AC]; 504 }; 505 506 /* per-frame tx control block */ 507 struct ath_tx_control { 508 - struct ath_node *an; /* destination to sent to */ 509 - int if_id; /* only valid for cab traffic */ 510 - int qnum; /* h/w queue number */ 511 - u32 ht:1; /* if it can be transmitted using HT */ 512 - u32 ps:1; /* if one or more stations are in PS mode */ 513 - u32 use_minrate:1; /* if this frame should transmitted using 514 - minimum rate */ 515 - enum ath9k_pkt_type atype; /* Atheros packet type */ 516 - enum ath9k_key_type keytype; /* key type */ 517 - u32 flags; /* HAL flags */ 518 - u16 seqno; /* sequence number */ 519 - u16 tidno; /* tid number */ 520 - u16 txpower; /* transmit power */ 521 - u16 frmlen; /* frame length */ 522 - u32 keyix; /* key index */ 523 - int min_rate; /* minimum rate */ 524 - int mcast_rate; /* multicast rate */ 525 - u16 nextfraglen; /* next fragment length */ 526 - /* below is set only by ath_dev */ 527 - struct ath_softc *dev; /* device handle */ 528 dma_addr_t dmacontext; 529 }; 530 531 /* per frame tx status block */ 532 struct ath_xmit_status { 533 - int retries; /* number of retries to successufully 534 - transmit this frame */ 535 - int flags; /* status of transmit */ 536 #define ATH_TX_ERROR 0x01 537 #define ATH_TX_XRETRY 0x02 538 #define ATH_TX_BAR 0x04 ··· 645 646 /* Per-node aggregation state */ 647 struct ath_node_aggr { 648 - struct ath_atx tx; /* node transmit state */ 649 - struct ath_arx rx; /* node receive state */ 650 }; 651 652 /* driver-specific node state */ 653 struct ath_node { 654 - struct list_head list; 655 - struct ath_softc *an_sc; /* back pointer */ 656 - atomic_t an_refcnt; 657 struct ath_chainmask_sel an_chainmask_sel; 658 - struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */ 659 - u8 an_smmode; /* SM Power save mode */ 660 - u8 an_flags; 661 - u8 an_addr[ETH_ALEN]; 662 }; 663 664 void ath_tx_resume_tid(struct ath_softc *sc, ··· 752 /* VAPs */ 753 /********/ 754 755 - #define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */ 756 - #define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */ 757 - /* STA only: the associated AP is HT capable */ 758 - #define ATH_IF_HT 0x0004 759 - /* AP/IBSS only: current BSS has privacy on */ 760 - #define ATH_IF_PRIVACY 0x0008 761 - #define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */ 762 - #define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */ 763 - 764 /* 765 * Define the scheme that we select MAC address for multiple 766 * BSS on the same radio. The very first VAP will just use the MAC ··· 771 772 /* driver-specific vap state */ 773 struct ath_vap { 774 - struct ieee80211_vif *av_if_data; /* interface(vap) 775 - instance from 802.11 protocal layer */ 776 - enum ath9k_opmode av_opmode; /* VAP operational mode */ 777 - struct ath_buf *av_bcbuf; /* beacon buffer */ 778 - struct ath_beacon_offset av_boff; /* dynamic update state */ 779 - struct ath_tx_control av_btxctl; /* tx control information 780 - for beacon */ 781 - int av_bslot; /* beacon slot index */ 782 - struct ath_txq av_mcastq; /* multicast 783 - transmit queue */ 784 - struct ath_vap_config av_config; /* vap configuration 785 - parameters from 802.11 protocol layer*/ 786 - struct ath_rate_node *rc_node; 787 }; 788 789 int ath_vap_attach(struct ath_softc *sc,
··· 51 52 /* Macro to expand scalars to 64-bit objects */ 53 54 + #define ito64(x) (sizeof(x) == 8) ? \ 55 + (((unsigned long long int)(x)) & (0xff)) : \ 56 + (sizeof(x) == 16) ? \ 57 + (((unsigned long long int)(x)) & 0xffff) : \ 58 + ((sizeof(x) == 32) ? \ 59 (((unsigned long long int)(x)) & 0xffffffff) : \ 60 + (unsigned long long int)(x)) 61 62 /* increment with wrap-around */ 63 + #define INCR(_l, _sz) do { \ 64 + (_l)++; \ 65 + (_l) &= ((_sz) - 1); \ 66 } while (0) 67 68 /* decrement with wrap-around */ 69 + #define DECR(_l, _sz) do { \ 70 + (_l)--; \ 71 + (_l) &= ((_sz) - 1); \ 72 } while (0) 73 74 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) ··· 136 /* Per-instance load-time (note: NOT run-time) configurations 137 * for Atheros Device */ 138 struct ath_config { 139 + u32 ath_aggr_prot; 140 + u16 txpowlimit; 141 + u16 txpowlimit_override; 142 + u8 cabqReadytime; /* Cabq Readytime % */ 143 + u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */ 144 }; 145 146 /***********************/ ··· 161 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35 162 /* Struct to store the chainmask select related info */ 163 struct ath_chainmask_sel { 164 + struct timer_list timer; 165 + int cur_tx_mask; /* user configured or 3x3 */ 166 + int cur_rx_mask; /* user configured or 3x3 */ 167 + int tx_avgrssi; 168 + u8 switch_allowed:1, /* timer will set this */ 169 + cm_sel_enabled : 1; 170 }; 171 172 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an); ··· 192 193 struct ath_buf_state { 194 int bfs_nframes; /* # frames in aggregate */ 195 + u16 bfs_al; /* length of aggregate */ 196 + u16 bfs_frmlen; /* length of frame */ 197 int bfs_seqno; /* sequence number */ 198 int bfs_tidno; /* tid of this frame */ 199 int bfs_retries; /* current retries */ ··· 205 u8 bfs_isretried:1; /* is retried */ 206 u8 bfs_isxretried:1; /* is excessive retried */ 207 u8 bfs_shpreamble:1; /* is short preamble */ 208 + u8 bfs_isbar:1; /* is a BAR */ 209 u8 bfs_ispspoll:1; /* is a PS-Poll */ 210 u8 bfs_aggrburst:1; /* is a aggr burst */ 211 u8 bfs_calcairtime:1; /* requests airtime be calculated ··· 247 struct list_head list; 248 struct list_head *last; 249 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 250 + an aggregate) */ 251 struct ath_buf *bf_lastfrm; /* last buf of this frame */ 252 struct ath_buf *bf_next; /* next subframe in the aggregate */ 253 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */ ··· 257 dma_addr_t bf_daddr; /* physical addr of desc */ 258 dma_addr_t bf_buf_addr; /* physical addr of data buffer */ 259 u32 bf_status; 260 + u16 bf_flags; /* tx descriptor flags */ 261 struct ath_buf_state bf_state; /* buffer state */ 262 dma_addr_t bf_dmacontext; 263 }; ··· 331 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 332 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 333 int8_t abs_rssi; /* absolute RSSI */ 334 + u8 rateieee; /* data rate received (IEEE rate code) */ 335 + u8 ratecode; /* phy rate code */ 336 int rateKbps; /* data rate received (Kbps) */ 337 int antenna; /* rx antenna */ 338 int flags; /* status of associated skb */ ··· 351 }; 352 353 struct ath_rxbuf { 354 + struct sk_buff *rx_wbuf; 355 + unsigned long rx_time; /* system time when received */ 356 + struct ath_recv_status rx_status; /* cached rx status */ 357 }; 358 359 /* Per-TID aggregate receiver state for a node */ 360 struct ath_arx_tid { 361 + struct ath_node *an; 362 + struct ath_rxbuf *rxbuf; /* re-ordering buffer */ 363 + struct timer_list timer; 364 + spinlock_t tidlock; 365 + int baw_head; /* seq_next at head */ 366 + int baw_tail; /* tail of block-ack window */ 367 + int seq_reset; /* need to reset start sequence */ 368 + int addba_exchangecomplete; 369 + u16 seq_next; /* next expected sequence */ 370 + u16 baw_size; /* block-ack window size */ 371 }; 372 373 /* Per-node receiver aggregate state */ 374 struct ath_arx { 375 + struct ath_arx_tid tid[WME_NUM_TID]; 376 }; 377 378 int ath_startrecv(struct ath_softc *sc); ··· 444 * hardware queue). 445 */ 446 struct ath_txq { 447 + u32 axq_qnum; /* hardware q number */ 448 + u32 *axq_link; /* link ptr in last TX desc */ 449 + struct list_head axq_q; /* transmit queue */ 450 + spinlock_t axq_lock; 451 + unsigned long axq_lockflags; /* intr state when must cli */ 452 + u32 axq_depth; /* queue depth */ 453 + u8 axq_aggr_depth; /* aggregates queued */ 454 + u32 axq_totalqueued; /* total ever queued */ 455 + 456 + /* count to determine if descriptor should generate int on this txq. */ 457 + u32 axq_intrcnt; 458 + 459 + bool stopped; /* Is mac80211 queue stopped ? */ 460 + struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ 461 + 462 + /* first desc of the last descriptor that contains CTS */ 463 + struct ath_desc *axq_lastdsWithCTS; 464 + 465 + /* final desc of the gating desc that determines whether 466 + lastdsWithCTS has been DMA'ed or not */ 467 + struct ath_desc *axq_gatingds; 468 + 469 + struct list_head axq_acq; 470 }; 471 472 /* per TID aggregate tx state for a destination */ 473 struct ath_atx_tid { 474 + struct list_head list; /* round-robin tid entry */ 475 + struct list_head buf_q; /* pending buffers */ 476 + struct ath_node *an; 477 + struct ath_atx_ac *ac; 478 + struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ 479 + u16 seq_start; 480 + u16 seq_next; 481 + u16 baw_size; 482 + int tidno; 483 + int baw_head; /* first un-acked tx buffer */ 484 + int baw_tail; /* next unused tx buffer slot */ 485 + int sched; 486 + int paused; 487 + int cleanup_inprogress; 488 + u32 addba_exchangecomplete:1; 489 + int32_t addba_exchangeinprogress; 490 + int addba_exchangeattempts; 491 }; 492 493 /* per access-category aggregate tx state for a destination */ 494 struct ath_atx_ac { 495 + int sched; /* dest-ac is scheduled */ 496 + int qnum; /* H/W queue number associated 497 + with this AC */ 498 + struct list_head list; /* round-robin txq entry */ 499 + struct list_head tid_q; /* queue of TIDs with buffers */ 500 }; 501 502 /* per dest tx state */ 503 struct ath_atx { 504 + struct ath_atx_tid tid[WME_NUM_TID]; 505 + struct ath_atx_ac ac[WME_NUM_AC]; 506 }; 507 508 /* per-frame tx control block */ 509 struct ath_tx_control { 510 + struct ath_node *an; 511 + int if_id; 512 + int qnum; 513 + u32 ht:1; 514 + u32 ps:1; 515 + u32 use_minrate:1; 516 + enum ath9k_pkt_type atype; 517 + enum ath9k_key_type keytype; 518 + u32 flags; 519 + u16 seqno; 520 + u16 tidno; 521 + u16 txpower; 522 + u16 frmlen; 523 + u32 keyix; 524 + int min_rate; 525 + int mcast_rate; 526 + u16 nextfraglen; 527 + struct ath_softc *dev; 528 dma_addr_t dmacontext; 529 }; 530 531 /* per frame tx status block */ 532 struct ath_xmit_status { 533 + int retries; /* number of retries to successufully 534 + transmit this frame */ 535 + int flags; /* status of transmit */ 536 #define ATH_TX_ERROR 0x01 537 #define ATH_TX_XRETRY 0x02 538 #define ATH_TX_BAR 0x04 ··· 647 648 /* Per-node aggregation state */ 649 struct ath_node_aggr { 650 + struct ath_atx tx; /* node transmit state */ 651 + struct ath_arx rx; /* node receive state */ 652 }; 653 654 /* driver-specific node state */ 655 struct ath_node { 656 + struct list_head list; 657 + struct ath_softc *an_sc; 658 + atomic_t an_refcnt; 659 struct ath_chainmask_sel an_chainmask_sel; 660 + struct ath_node_aggr an_aggr; 661 + u8 an_smmode; /* SM Power save mode */ 662 + u8 an_flags; 663 + u8 an_addr[ETH_ALEN]; 664 }; 665 666 void ath_tx_resume_tid(struct ath_softc *sc, ··· 754 /* VAPs */ 755 /********/ 756 757 /* 758 * Define the scheme that we select MAC address for multiple 759 * BSS on the same radio. The very first VAP will just use the MAC ··· 782 783 /* driver-specific vap state */ 784 struct ath_vap { 785 + struct ieee80211_vif *av_if_data; 786 + enum ath9k_opmode av_opmode; /* VAP operational mode */ 787 + struct ath_buf *av_bcbuf; /* beacon buffer */ 788 + struct ath_beacon_offset av_boff; /* dynamic update state */ 789 + struct ath_tx_control av_btxctl; /* txctl information for beacon */ 790 + int av_bslot; /* beacon slot index */ 791 + struct ath_txq av_mcastq; /* multicast transmit queue */ 792 + struct ath_vap_config av_config;/* vap configuration parameters*/ 793 + struct ath_rate_node *rc_node; 794 }; 795 796 int ath_vap_attach(struct ath_softc *sc,