···5152/* Macro to expand scalars to 64-bit objects */5354-#define ito64(x) (sizeof(x) == 8) ? \55- (((unsigned long long int)(x)) & (0xff)) : \56- (sizeof(x) == 16) ? \57- (((unsigned long long int)(x)) & 0xffff) : \58- ((sizeof(x) == 32) ? \59 (((unsigned long long int)(x)) & 0xffffffff) : \60- (unsigned long long int)(x))6162/* increment with wrap-around */63-#define INCR(_l, _sz) do { \64- (_l)++; \65- (_l) &= ((_sz) - 1); \66 } while (0)6768/* decrement with wrap-around */69-#define DECR(_l, _sz) do { \70- (_l)--; \71- (_l) &= ((_sz) - 1); \72 } while (0)7374#define A_MAX(a, b) ((a) > (b) ? (a) : (b))···136/* Per-instance load-time (note: NOT run-time) configurations137 * for Atheros Device */138struct ath_config {139- u32 ath_aggr_prot;140- u16 txpowlimit;141- u16 txpowlimit_override;142- u8 cabqReadytime; /* Cabq Readytime % */143- u8 swBeaconProcess; /* Process received beacons144- in SW (vs HW) */145};146147/***********************/···160#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35161/* Struct to store the chainmask select related info */162struct ath_chainmask_sel {163- struct timer_list timer;164- int cur_tx_mask; /* user configured or 3x3 */165- int cur_rx_mask; /* user configured or 3x3 */166- int tx_avgrssi;167- u8 switch_allowed:1, /* timer will set this */168- cm_sel_enabled:1;169};170171int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);···191192struct ath_buf_state {193 int bfs_nframes; /* # frames in aggregate */194- u16 bfs_al; /* length of aggregate */195- u16 bfs_frmlen; /* length of frame */196 int bfs_seqno; /* sequence number */197 int bfs_tidno; /* tid of this frame */198 int bfs_retries; /* current retries */···204 u8 bfs_isretried:1; /* is retried */205 u8 bfs_isxretried:1; /* is excessive retried */206 u8 bfs_shpreamble:1; /* is short preamble */207- u8 bfs_isbar:1; /* is a BAR */208 u8 bfs_ispspoll:1; /* is a PS-Poll */209 u8 bfs_aggrburst:1; /* is a aggr burst */210 u8 bfs_calcairtime:1; /* requests airtime be calculated···246 struct list_head list;247 struct list_head *last;248 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or249- an aggregate) */250 struct ath_buf *bf_lastfrm; /* last buf of this frame */251 struct ath_buf *bf_next; /* next subframe in the aggregate */252 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */···256 dma_addr_t bf_daddr; /* physical addr of desc */257 dma_addr_t bf_buf_addr; /* physical addr of data buffer */258 u32 bf_status;259- u16 bf_flags; /* tx descriptor flags */260 struct ath_buf_state bf_state; /* buffer state */261 dma_addr_t bf_dmacontext;262};···330 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */331 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */332 int8_t abs_rssi; /* absolute RSSI */333- u8 rateieee; /* data rate received (IEEE rate code) */334- u8 ratecode; /* phy rate code */335 int rateKbps; /* data rate received (Kbps) */336 int antenna; /* rx antenna */337 int flags; /* status of associated skb */···350};351352struct ath_rxbuf {353- struct sk_buff *rx_wbuf; /* buffer */354- unsigned long rx_time; /* system time when received */355- struct ath_recv_status rx_status; /* cached rx status */356};357358/* Per-TID aggregate receiver state for a node */359struct ath_arx_tid {360- struct ath_node *an; /* parent ath node */361- struct ath_rxbuf *rxbuf; /* re-ordering buffer */362- struct timer_list timer;363- spinlock_t tidlock; /* lock to protect this TID structure */364- int baw_head; /* seq_next at head */365- int baw_tail; /* tail of block-ack window */366- int seq_reset; /* need to reset start sequence */367- int addba_exchangecomplete;368- u16 seq_next; /* next expected sequence */369- u16 baw_size; /* block-ack window size */370};371372/* Per-node receiver aggregate state */373struct ath_arx {374- struct ath_arx_tid tid[WME_NUM_TID];375};376377int ath_startrecv(struct ath_softc *sc);···443 * hardware queue).444 */445struct ath_txq {446- u32 axq_qnum; /* hardware q number */447- u32 *axq_link; /* link ptr in last TX desc */448- struct list_head axq_q; /* transmit queue */449- spinlock_t axq_lock; /* lock on q and link */450- unsigned long axq_lockflags; /* intr state when must cli */451- u32 axq_depth; /* queue depth */452- u8 axq_aggr_depth; /* aggregates queued */453- u32 axq_totalqueued;/* total ever queued */454- u32 axq_intrcnt; /* count to determine455- if descriptor should generate456- int on this txq. */457- bool stopped; /* Is mac80211 queue458- stopped ? */459- /* State for patching up CTS when bursting */460- struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/461- struct ath_desc *axq_lastdsWithCTS; /* first desc of the462- last descriptor that contains CTS */463- struct ath_desc *axq_gatingds; /* final desc of the gating desc464- * that determines whether lastdsWithCTS has465- * been DMA'ed or not */466- struct list_head axq_acq;00467};468469/* per TID aggregate tx state for a destination */470struct ath_atx_tid {471- struct list_head list; /* round-robin tid entry */472- struct list_head buf_q; /* pending buffers */473- struct ath_node *an; /* parent node structure */474- struct ath_atx_ac *ac; /* parent access category */475- struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */476- u16 seq_start; /* starting seq of BA window */477- u16 seq_next; /* next seq to be used */478- u16 baw_size; /* BA window size */479- int tidno; /* TID number */480- int baw_head; /* first un-acked tx buffer */481- int baw_tail; /* next unused tx buffer slot */482- int sched; /* TID is scheduled */483- int paused; /* TID is paused */484- int cleanup_inprogress; /* aggr of this TID is485- being teared down */486- u32 addba_exchangecomplete:1; /* ADDBA state */487- int32_t addba_exchangeinprogress;488- int addba_exchangeattempts;489};490491/* per access-category aggregate tx state for a destination */492struct ath_atx_ac {493- int sched; /* dest-ac is scheduled */494- int qnum; /* H/W queue number associated495- with this AC */496- struct list_head list; /* round-robin txq entry */497- struct list_head tid_q; /* queue of TIDs with buffers */498};499500/* per dest tx state */501struct ath_atx {502- struct ath_atx_tid tid[WME_NUM_TID];503- struct ath_atx_ac ac[WME_NUM_AC];504};505506/* per-frame tx control block */507struct ath_tx_control {508- struct ath_node *an; /* destination to sent to */509- int if_id; /* only valid for cab traffic */510- int qnum; /* h/w queue number */511- u32 ht:1; /* if it can be transmitted using HT */512- u32 ps:1; /* if one or more stations are in PS mode */513- u32 use_minrate:1; /* if this frame should transmitted using514- minimum rate */515- enum ath9k_pkt_type atype; /* Atheros packet type */516- enum ath9k_key_type keytype; /* key type */517- u32 flags; /* HAL flags */518- u16 seqno; /* sequence number */519- u16 tidno; /* tid number */520- u16 txpower; /* transmit power */521- u16 frmlen; /* frame length */522- u32 keyix; /* key index */523- int min_rate; /* minimum rate */524- int mcast_rate; /* multicast rate */525- u16 nextfraglen; /* next fragment length */526- /* below is set only by ath_dev */527- struct ath_softc *dev; /* device handle */528 dma_addr_t dmacontext;529};530531/* per frame tx status block */532struct ath_xmit_status {533- int retries; /* number of retries to successufully534- transmit this frame */535- int flags; /* status of transmit */536#define ATH_TX_ERROR 0x01537#define ATH_TX_XRETRY 0x02538#define ATH_TX_BAR 0x04···645646/* Per-node aggregation state */647struct ath_node_aggr {648- struct ath_atx tx; /* node transmit state */649- struct ath_arx rx; /* node receive state */650};651652/* driver-specific node state */653struct ath_node {654- struct list_head list;655- struct ath_softc *an_sc; /* back pointer */656- atomic_t an_refcnt;657 struct ath_chainmask_sel an_chainmask_sel;658- struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */659- u8 an_smmode; /* SM Power save mode */660- u8 an_flags;661- u8 an_addr[ETH_ALEN];662};663664void ath_tx_resume_tid(struct ath_softc *sc,···752/* VAPs */753/********/754755-#define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */756-#define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */757-/* STA only: the associated AP is HT capable */758-#define ATH_IF_HT 0x0004759-/* AP/IBSS only: current BSS has privacy on */760-#define ATH_IF_PRIVACY 0x0008761-#define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */762-#define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */763-764/*765 * Define the scheme that we select MAC address for multiple766 * BSS on the same radio. The very first VAP will just use the MAC···771772/* driver-specific vap state */773struct ath_vap {774- struct ieee80211_vif *av_if_data; /* interface(vap)775- instance from 802.11 protocal layer */776- enum ath9k_opmode av_opmode; /* VAP operational mode */777- struct ath_buf *av_bcbuf; /* beacon buffer */778- struct ath_beacon_offset av_boff; /* dynamic update state */779- struct ath_tx_control av_btxctl; /* tx control information780- for beacon */781- int av_bslot; /* beacon slot index */782- struct ath_txq av_mcastq; /* multicast783- transmit queue */784- struct ath_vap_config av_config; /* vap configuration785- parameters from 802.11 protocol layer*/786- struct ath_rate_node *rc_node;787};788789int ath_vap_attach(struct ath_softc *sc,
···5152/* Macro to expand scalars to 64-bit objects */5354+#define ito64(x) (sizeof(x) == 8) ? \55+ (((unsigned long long int)(x)) & (0xff)) : \56+ (sizeof(x) == 16) ? \57+ (((unsigned long long int)(x)) & 0xffff) : \58+ ((sizeof(x) == 32) ? \59 (((unsigned long long int)(x)) & 0xffffffff) : \60+ (unsigned long long int)(x))6162/* increment with wrap-around */63+#define INCR(_l, _sz) do { \64+ (_l)++; \65+ (_l) &= ((_sz) - 1); \66 } while (0)6768/* decrement with wrap-around */69+#define DECR(_l, _sz) do { \70+ (_l)--; \71+ (_l) &= ((_sz) - 1); \72 } while (0)7374#define A_MAX(a, b) ((a) > (b) ? (a) : (b))···136/* Per-instance load-time (note: NOT run-time) configurations137 * for Atheros Device */138struct ath_config {139+ u32 ath_aggr_prot;140+ u16 txpowlimit;141+ u16 txpowlimit_override;142+ u8 cabqReadytime; /* Cabq Readytime % */143+ u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */0144};145146/***********************/···161#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35162/* Struct to store the chainmask select related info */163struct ath_chainmask_sel {164+ struct timer_list timer;165+ int cur_tx_mask; /* user configured or 3x3 */166+ int cur_rx_mask; /* user configured or 3x3 */167+ int tx_avgrssi;168+ u8 switch_allowed:1, /* timer will set this */169+ cm_sel_enabled : 1;170};171172int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);···192193struct ath_buf_state {194 int bfs_nframes; /* # frames in aggregate */195+ u16 bfs_al; /* length of aggregate */196+ u16 bfs_frmlen; /* length of frame */197 int bfs_seqno; /* sequence number */198 int bfs_tidno; /* tid of this frame */199 int bfs_retries; /* current retries */···205 u8 bfs_isretried:1; /* is retried */206 u8 bfs_isxretried:1; /* is excessive retried */207 u8 bfs_shpreamble:1; /* is short preamble */208+ u8 bfs_isbar:1; /* is a BAR */209 u8 bfs_ispspoll:1; /* is a PS-Poll */210 u8 bfs_aggrburst:1; /* is a aggr burst */211 u8 bfs_calcairtime:1; /* requests airtime be calculated···247 struct list_head list;248 struct list_head *last;249 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or250+ an aggregate) */251 struct ath_buf *bf_lastfrm; /* last buf of this frame */252 struct ath_buf *bf_next; /* next subframe in the aggregate */253 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */···257 dma_addr_t bf_daddr; /* physical addr of desc */258 dma_addr_t bf_buf_addr; /* physical addr of data buffer */259 u32 bf_status;260+ u16 bf_flags; /* tx descriptor flags */261 struct ath_buf_state bf_state; /* buffer state */262 dma_addr_t bf_dmacontext;263};···331 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */332 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */333 int8_t abs_rssi; /* absolute RSSI */334+ u8 rateieee; /* data rate received (IEEE rate code) */335+ u8 ratecode; /* phy rate code */336 int rateKbps; /* data rate received (Kbps) */337 int antenna; /* rx antenna */338 int flags; /* status of associated skb */···351};352353struct ath_rxbuf {354+ struct sk_buff *rx_wbuf;355+ unsigned long rx_time; /* system time when received */356+ struct ath_recv_status rx_status; /* cached rx status */357};358359/* Per-TID aggregate receiver state for a node */360struct ath_arx_tid {361+ struct ath_node *an;362+ struct ath_rxbuf *rxbuf; /* re-ordering buffer */363+ struct timer_list timer;364+ spinlock_t tidlock;365+ int baw_head; /* seq_next at head */366+ int baw_tail; /* tail of block-ack window */367+ int seq_reset; /* need to reset start sequence */368+ int addba_exchangecomplete;369+ u16 seq_next; /* next expected sequence */370+ u16 baw_size; /* block-ack window size */371};372373/* Per-node receiver aggregate state */374struct ath_arx {375+ struct ath_arx_tid tid[WME_NUM_TID];376};377378int ath_startrecv(struct ath_softc *sc);···444 * hardware queue).445 */446struct ath_txq {447+ u32 axq_qnum; /* hardware q number */448+ u32 *axq_link; /* link ptr in last TX desc */449+ struct list_head axq_q; /* transmit queue */450+ spinlock_t axq_lock;451+ unsigned long axq_lockflags; /* intr state when must cli */452+ u32 axq_depth; /* queue depth */453+ u8 axq_aggr_depth; /* aggregates queued */454+ u32 axq_totalqueued; /* total ever queued */455+456+ /* count to determine if descriptor should generate int on this txq. */457+ u32 axq_intrcnt;458+459+ bool stopped; /* Is mac80211 queue stopped ? */460+ struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/461+462+ /* first desc of the last descriptor that contains CTS */463+ struct ath_desc *axq_lastdsWithCTS;464+465+ /* final desc of the gating desc that determines whether466+ lastdsWithCTS has been DMA'ed or not */467+ struct ath_desc *axq_gatingds;468+469+ struct list_head axq_acq;470};471472/* per TID aggregate tx state for a destination */473struct ath_atx_tid {474+ struct list_head list; /* round-robin tid entry */475+ struct list_head buf_q; /* pending buffers */476+ struct ath_node *an;477+ struct ath_atx_ac *ac;478+ struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */479+ u16 seq_start;480+ u16 seq_next;481+ u16 baw_size;482+ int tidno;483+ int baw_head; /* first un-acked tx buffer */484+ int baw_tail; /* next unused tx buffer slot */485+ int sched;486+ int paused;487+ int cleanup_inprogress;488+ u32 addba_exchangecomplete:1;489+ int32_t addba_exchangeinprogress;490+ int addba_exchangeattempts;0491};492493/* per access-category aggregate tx state for a destination */494struct ath_atx_ac {495+ int sched; /* dest-ac is scheduled */496+ int qnum; /* H/W queue number associated497+ with this AC */498+ struct list_head list; /* round-robin txq entry */499+ struct list_head tid_q; /* queue of TIDs with buffers */500};501502/* per dest tx state */503struct ath_atx {504+ struct ath_atx_tid tid[WME_NUM_TID];505+ struct ath_atx_ac ac[WME_NUM_AC];506};507508/* per-frame tx control block */509struct ath_tx_control {510+ struct ath_node *an;511+ int if_id;512+ int qnum;513+ u32 ht:1;514+ u32 ps:1;515+ u32 use_minrate:1;516+ enum ath9k_pkt_type atype;517+ enum ath9k_key_type keytype;518+ u32 flags;519+ u16 seqno;520+ u16 tidno;521+ u16 txpower;522+ u16 frmlen;523+ u32 keyix;524+ int min_rate;525+ int mcast_rate;526+ u16 nextfraglen;527+ struct ath_softc *dev;00528 dma_addr_t dmacontext;529};530531/* per frame tx status block */532struct ath_xmit_status {533+ int retries; /* number of retries to successufully534+ transmit this frame */535+ int flags; /* status of transmit */536#define ATH_TX_ERROR 0x01537#define ATH_TX_XRETRY 0x02538#define ATH_TX_BAR 0x04···647648/* Per-node aggregation state */649struct ath_node_aggr {650+ struct ath_atx tx; /* node transmit state */651+ struct ath_arx rx; /* node receive state */652};653654/* driver-specific node state */655struct ath_node {656+ struct list_head list;657+ struct ath_softc *an_sc;658+ atomic_t an_refcnt;659 struct ath_chainmask_sel an_chainmask_sel;660+ struct ath_node_aggr an_aggr;661+ u8 an_smmode; /* SM Power save mode */662+ u8 an_flags;663+ u8 an_addr[ETH_ALEN];664};665666void ath_tx_resume_tid(struct ath_softc *sc,···754/* VAPs */755/********/756000000000757/*758 * Define the scheme that we select MAC address for multiple759 * BSS on the same radio. The very first VAP will just use the MAC···782783/* driver-specific vap state */784struct ath_vap {785+ struct ieee80211_vif *av_if_data;786+ enum ath9k_opmode av_opmode; /* VAP operational mode */787+ struct ath_buf *av_bcbuf; /* beacon buffer */788+ struct ath_beacon_offset av_boff; /* dynamic update state */789+ struct ath_tx_control av_btxctl; /* txctl information for beacon */790+ int av_bslot; /* beacon slot index */791+ struct ath_txq av_mcastq; /* multicast transmit queue */792+ struct ath_vap_config av_config;/* vap configuration parameters*/793+ struct ath_rate_node *rc_node;0000794};795796int ath_vap_attach(struct ath_softc *sc,