···51515252/* Macro to expand scalars to 64-bit objects */53535454-#define ito64(x) (sizeof(x) == 8) ? \5555- (((unsigned long long int)(x)) & (0xff)) : \5656- (sizeof(x) == 16) ? \5757- (((unsigned long long int)(x)) & 0xffff) : \5858- ((sizeof(x) == 32) ? \5454+#define ito64(x) (sizeof(x) == 8) ? \5555+ (((unsigned long long int)(x)) & (0xff)) : \5656+ (sizeof(x) == 16) ? \5757+ (((unsigned long long int)(x)) & 0xffff) : \5858+ ((sizeof(x) == 32) ? \5959 (((unsigned long long int)(x)) & 0xffffffff) : \6060- (unsigned long long int)(x))6060+ (unsigned long long int)(x))61616262/* increment with wrap-around */6363-#define INCR(_l, _sz) do { \6464- (_l)++; \6565- (_l) &= ((_sz) - 1); \6363+#define INCR(_l, _sz) do { \6464+ (_l)++; \6565+ (_l) &= ((_sz) - 1); \6666 } while (0)67676868/* decrement with wrap-around */6969-#define DECR(_l, _sz) do { \7070- (_l)--; \7171- (_l) &= ((_sz) - 1); \6969+#define DECR(_l, _sz) do { \7070+ (_l)--; \7171+ (_l) &= ((_sz) - 1); \7272 } while (0)73737474#define A_MAX(a, b) ((a) > (b) ? (a) : (b))···136136/* Per-instance load-time (note: NOT run-time) configurations137137 * for Atheros Device */138138struct ath_config {139139- u32 ath_aggr_prot;140140- u16 txpowlimit;141141- u16 txpowlimit_override;142142- u8 cabqReadytime; /* Cabq Readytime % */143143- u8 swBeaconProcess; /* Process received beacons144144- in SW (vs HW) */139139+ u32 ath_aggr_prot;140140+ u16 txpowlimit;141141+ u16 txpowlimit_override;142142+ u8 cabqReadytime; /* Cabq Readytime % */143143+ u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */145144};146145147146/***********************/···160161#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35161162/* Struct to store the chainmask select related info */162163struct ath_chainmask_sel {163163- struct timer_list timer;164164- int cur_tx_mask; /* user configured or 3x3 */165165- int cur_rx_mask; /* user configured or 3x3 */166166- int tx_avgrssi;167167- u8 switch_allowed:1, /* timer will set this */168168- cm_sel_enabled:1;164164+ struct timer_list timer;165165+ int cur_tx_mask; /* user configured or 3x3 */166166+ int cur_rx_mask; /* user configured or 3x3 */167167+ int tx_avgrssi;168168+ u8 switch_allowed:1, /* timer will set this */169169+ cm_sel_enabled : 1;169170};170171171172int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);···191192192193struct ath_buf_state {193194 int bfs_nframes; /* # frames in aggregate */194194- u16 bfs_al; /* length of aggregate */195195- u16 bfs_frmlen; /* length of frame */195195+ u16 bfs_al; /* length of aggregate */196196+ u16 bfs_frmlen; /* length of frame */196197 int bfs_seqno; /* sequence number */197198 int bfs_tidno; /* tid of this frame */198199 int bfs_retries; /* current retries */···204205 u8 bfs_isretried:1; /* is retried */205206 u8 bfs_isxretried:1; /* is excessive retried */206207 u8 bfs_shpreamble:1; /* is short preamble */207207- u8 bfs_isbar:1; /* is a BAR */208208+ u8 bfs_isbar:1; /* is a BAR */208209 u8 bfs_ispspoll:1; /* is a PS-Poll */209210 u8 bfs_aggrburst:1; /* is a aggr burst */210211 u8 bfs_calcairtime:1; /* requests airtime be calculated···246247 struct list_head list;247248 struct list_head *last;248249 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or249249- an aggregate) */250250+ an aggregate) */250251 struct ath_buf *bf_lastfrm; /* last buf of this frame */251252 struct ath_buf *bf_next; /* next subframe in the aggregate */252253 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */···256257 dma_addr_t bf_daddr; /* physical addr of desc */257258 dma_addr_t bf_buf_addr; /* physical addr of data buffer */258259 u32 bf_status;259259- u16 bf_flags; /* tx descriptor flags */260260+ u16 bf_flags; /* tx descriptor flags */260261 struct ath_buf_state bf_state; /* buffer state */261262 dma_addr_t bf_dmacontext;262263};···330331 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */331332 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */332333 int8_t abs_rssi; /* absolute RSSI */333333- u8 rateieee; /* data rate received (IEEE rate code) */334334- u8 ratecode; /* phy rate code */334334+ u8 rateieee; /* data rate received (IEEE rate code) */335335+ u8 ratecode; /* phy rate code */335336 int rateKbps; /* data rate received (Kbps) */336337 int antenna; /* rx antenna */337338 int flags; /* status of associated skb */···350351};351352352353struct ath_rxbuf {353353- struct sk_buff *rx_wbuf; /* buffer */354354- unsigned long rx_time; /* system time when received */355355- struct ath_recv_status rx_status; /* cached rx status */354354+ struct sk_buff *rx_wbuf;355355+ unsigned long rx_time; /* system time when received */356356+ struct ath_recv_status rx_status; /* cached rx status */356357};357358358359/* Per-TID aggregate receiver state for a node */359360struct ath_arx_tid {360360- struct ath_node *an; /* parent ath node */361361- struct ath_rxbuf *rxbuf; /* re-ordering buffer */362362- struct timer_list timer;363363- spinlock_t tidlock; /* lock to protect this TID structure */364364- int baw_head; /* seq_next at head */365365- int baw_tail; /* tail of block-ack window */366366- int seq_reset; /* need to reset start sequence */367367- int addba_exchangecomplete;368368- u16 seq_next; /* next expected sequence */369369- u16 baw_size; /* block-ack window size */361361+ struct ath_node *an;362362+ struct ath_rxbuf *rxbuf; /* re-ordering buffer */363363+ struct timer_list timer;364364+ spinlock_t tidlock;365365+ int baw_head; /* seq_next at head */366366+ int baw_tail; /* tail of block-ack window */367367+ int seq_reset; /* need to reset start sequence */368368+ int addba_exchangecomplete;369369+ u16 seq_next; /* next expected sequence */370370+ u16 baw_size; /* block-ack window size */370371};371372372373/* Per-node receiver aggregate state */373374struct ath_arx {374374- struct ath_arx_tid tid[WME_NUM_TID];375375+ struct ath_arx_tid tid[WME_NUM_TID];375376};376377377378int ath_startrecv(struct ath_softc *sc);···443444 * hardware queue).444445 */445446struct ath_txq {446446- u32 axq_qnum; /* hardware q number */447447- u32 *axq_link; /* link ptr in last TX desc */448448- struct list_head axq_q; /* transmit queue */449449- spinlock_t axq_lock; /* lock on q and link */450450- unsigned long axq_lockflags; /* intr state when must cli */451451- u32 axq_depth; /* queue depth */452452- u8 axq_aggr_depth; /* aggregates queued */453453- u32 axq_totalqueued;/* total ever queued */454454- u32 axq_intrcnt; /* count to determine455455- if descriptor should generate456456- int on this txq. */457457- bool stopped; /* Is mac80211 queue458458- stopped ? */459459- /* State for patching up CTS when bursting */460460- struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/461461- struct ath_desc *axq_lastdsWithCTS; /* first desc of the462462- last descriptor that contains CTS */463463- struct ath_desc *axq_gatingds; /* final desc of the gating desc464464- * that determines whether lastdsWithCTS has465465- * been DMA'ed or not */466466- struct list_head axq_acq;447447+ u32 axq_qnum; /* hardware q number */448448+ u32 *axq_link; /* link ptr in last TX desc */449449+ struct list_head axq_q; /* transmit queue */450450+ spinlock_t axq_lock;451451+ unsigned long axq_lockflags; /* intr state when must cli */452452+ u32 axq_depth; /* queue depth */453453+ u8 axq_aggr_depth; /* aggregates queued */454454+ u32 axq_totalqueued; /* total ever queued */455455+456456+ /* count to determine if descriptor should generate int on this txq. */457457+ u32 axq_intrcnt;458458+459459+ bool stopped; /* Is mac80211 queue stopped ? */460460+ struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/461461+462462+ /* first desc of the last descriptor that contains CTS */463463+ struct ath_desc *axq_lastdsWithCTS;464464+465465+ /* final desc of the gating desc that determines whether466466+ lastdsWithCTS has been DMA'ed or not */467467+ struct ath_desc *axq_gatingds;468468+469469+ struct list_head axq_acq;467470};468471469472/* per TID aggregate tx state for a destination */470473struct ath_atx_tid {471471- struct list_head list; /* round-robin tid entry */472472- struct list_head buf_q; /* pending buffers */473473- struct ath_node *an; /* parent node structure */474474- struct ath_atx_ac *ac; /* parent access category */475475- struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */476476- u16 seq_start; /* starting seq of BA window */477477- u16 seq_next; /* next seq to be used */478478- u16 baw_size; /* BA window size */479479- int tidno; /* TID number */480480- int baw_head; /* first un-acked tx buffer */481481- int baw_tail; /* next unused tx buffer slot */482482- int sched; /* TID is scheduled */483483- int paused; /* TID is paused */484484- int cleanup_inprogress; /* aggr of this TID is485485- being teared down */486486- u32 addba_exchangecomplete:1; /* ADDBA state */487487- int32_t addba_exchangeinprogress;488488- int addba_exchangeattempts;474474+ struct list_head list; /* round-robin tid entry */475475+ struct list_head buf_q; /* pending buffers */476476+ struct ath_node *an;477477+ struct ath_atx_ac *ac;478478+ struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */479479+ u16 seq_start;480480+ u16 seq_next;481481+ u16 baw_size;482482+ int tidno;483483+ int baw_head; /* first un-acked tx buffer */484484+ int baw_tail; /* next unused tx buffer slot */485485+ int sched;486486+ int paused;487487+ int cleanup_inprogress;488488+ u32 addba_exchangecomplete:1;489489+ int32_t addba_exchangeinprogress;490490+ int addba_exchangeattempts;489491};490492491493/* per access-category aggregate tx state for a destination */492494struct ath_atx_ac {493493- int sched; /* dest-ac is scheduled */494494- int qnum; /* H/W queue number associated495495- with this AC */496496- struct list_head list; /* round-robin txq entry */497497- struct list_head tid_q; /* queue of TIDs with buffers */495495+ int sched; /* dest-ac is scheduled */496496+ int qnum; /* H/W queue number associated497497+ with this AC */498498+ struct list_head list; /* round-robin txq entry */499499+ struct list_head tid_q; /* queue of TIDs with buffers */498500};499501500502/* per dest tx state */501503struct ath_atx {502502- struct ath_atx_tid tid[WME_NUM_TID];503503- struct ath_atx_ac ac[WME_NUM_AC];504504+ struct ath_atx_tid tid[WME_NUM_TID];505505+ struct ath_atx_ac ac[WME_NUM_AC];504506};505507506508/* per-frame tx control block */507509struct ath_tx_control {508508- struct ath_node *an; /* destination to sent to */509509- int if_id; /* only valid for cab traffic */510510- int qnum; /* h/w queue number */511511- u32 ht:1; /* if it can be transmitted using HT */512512- u32 ps:1; /* if one or more stations are in PS mode */513513- u32 use_minrate:1; /* if this frame should transmitted using514514- minimum rate */515515- enum ath9k_pkt_type atype; /* Atheros packet type */516516- enum ath9k_key_type keytype; /* key type */517517- u32 flags; /* HAL flags */518518- u16 seqno; /* sequence number */519519- u16 tidno; /* tid number */520520- u16 txpower; /* transmit power */521521- u16 frmlen; /* frame length */522522- u32 keyix; /* key index */523523- int min_rate; /* minimum rate */524524- int mcast_rate; /* multicast rate */525525- u16 nextfraglen; /* next fragment length */526526- /* below is set only by ath_dev */527527- struct ath_softc *dev; /* device handle */510510+ struct ath_node *an;511511+ int if_id;512512+ int qnum;513513+ u32 ht:1;514514+ u32 ps:1;515515+ u32 use_minrate:1;516516+ enum ath9k_pkt_type atype;517517+ enum ath9k_key_type keytype;518518+ u32 flags;519519+ u16 seqno;520520+ u16 tidno;521521+ u16 txpower;522522+ u16 frmlen;523523+ u32 keyix;524524+ int min_rate;525525+ int mcast_rate;526526+ u16 nextfraglen;527527+ struct ath_softc *dev;528528 dma_addr_t dmacontext;529529};530530531531/* per frame tx status block */532532struct ath_xmit_status {533533- int retries; /* number of retries to successufully534534- transmit this frame */535535- int flags; /* status of transmit */533533+ int retries; /* number of retries to successufully534534+ transmit this frame */535535+ int flags; /* status of transmit */536536#define ATH_TX_ERROR 0x01537537#define ATH_TX_XRETRY 0x02538538#define ATH_TX_BAR 0x04···645647646648/* Per-node aggregation state */647649struct ath_node_aggr {648648- struct ath_atx tx; /* node transmit state */649649- struct ath_arx rx; /* node receive state */650650+ struct ath_atx tx; /* node transmit state */651651+ struct ath_arx rx; /* node receive state */650652};651653652654/* driver-specific node state */653655struct ath_node {654654- struct list_head list;655655- struct ath_softc *an_sc; /* back pointer */656656- atomic_t an_refcnt;656656+ struct list_head list;657657+ struct ath_softc *an_sc;658658+ atomic_t an_refcnt;657659 struct ath_chainmask_sel an_chainmask_sel;658658- struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */659659- u8 an_smmode; /* SM Power save mode */660660- u8 an_flags;661661- u8 an_addr[ETH_ALEN];660660+ struct ath_node_aggr an_aggr;661661+ u8 an_smmode; /* SM Power save mode */662662+ u8 an_flags;663663+ u8 an_addr[ETH_ALEN];662664};663665664666void ath_tx_resume_tid(struct ath_softc *sc,···752754/* VAPs */753755/********/754756755755-#define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */756756-#define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */757757-/* STA only: the associated AP is HT capable */758758-#define ATH_IF_HT 0x0004759759-/* AP/IBSS only: current BSS has privacy on */760760-#define ATH_IF_PRIVACY 0x0008761761-#define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */762762-#define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */763763-764757/*765758 * Define the scheme that we select MAC address for multiple766759 * BSS on the same radio. The very first VAP will just use the MAC···771782772783/* driver-specific vap state */773784struct ath_vap {774774- struct ieee80211_vif *av_if_data; /* interface(vap)775775- instance from 802.11 protocal layer */776776- enum ath9k_opmode av_opmode; /* VAP operational mode */777777- struct ath_buf *av_bcbuf; /* beacon buffer */778778- struct ath_beacon_offset av_boff; /* dynamic update state */779779- struct ath_tx_control av_btxctl; /* tx control information780780- for beacon */781781- int av_bslot; /* beacon slot index */782782- struct ath_txq av_mcastq; /* multicast783783- transmit queue */784784- struct ath_vap_config av_config; /* vap configuration785785- parameters from 802.11 protocol layer*/786786- struct ath_rate_node *rc_node;785785+ struct ieee80211_vif *av_if_data;786786+ enum ath9k_opmode av_opmode; /* VAP operational mode */787787+ struct ath_buf *av_bcbuf; /* beacon buffer */788788+ struct ath_beacon_offset av_boff; /* dynamic update state */789789+ struct ath_tx_control av_btxctl; /* txctl information for beacon */790790+ int av_bslot; /* beacon slot index */791791+ struct ath_txq av_mcastq; /* multicast transmit queue */792792+ struct ath_vap_config av_config;/* vap configuration parameters*/793793+ struct ath_rate_node *rc_node;787794};788795789796int ath_vap_attach(struct ath_softc *sc,