tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
reset: qcom: PDC Global (Power Domain Controller) reset controller
Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
authored by
Sibi Sankar
and committed by
Philipp Zabel
eea2926b
032f1163
+134
+9
drivers/reset/Kconfig
+9
drivers/reset/Kconfig
···
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reset signals provided by AOSS for Modem, Venus, ADSP,
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GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
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config RESET_QCOM_PDC
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tristate "Qualcomm PDC Reset Driver"
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depends on ARCH_QCOM || COMPILE_TEST
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help
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This enables the PDC (Power Domain Controller) reset driver
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for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
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to control reset signals provided by PDC for Modem, Compute,
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Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
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drivers/reset/Makefile
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drivers/reset/Makefile
···
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
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obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+124
drivers/reset/reset-qcom-pdc.c
+124
drivers/reset/reset-qcom-pdc.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/qcom,sdm845-pdc.h>
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#define RPMH_PDC_SYNC_RESET 0x100
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struct qcom_pdc_reset_map {
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u8 bit;
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};
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struct qcom_pdc_reset_data {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static const struct regmap_config sdm845_pdc_regmap_config = {
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.name = "pdc-reset",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x20000,
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.fast_io = true,
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};
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static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
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[PDC_APPS_SYNC_RESET] = {0},
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[PDC_SP_SYNC_RESET] = {1},
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[PDC_AUDIO_SYNC_RESET] = {2},
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[PDC_SENSORS_SYNC_RESET] = {3},
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[PDC_AOP_SYNC_RESET] = {4},
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[PDC_DEBUG_SYNC_RESET] = {5},
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[PDC_GPU_SYNC_RESET] = {6},
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[PDC_DISPLAY_SYNC_RESET] = {7},
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[PDC_COMPUTE_SYNC_RESET] = {8},
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[PDC_MODEM_SYNC_RESET] = {9},
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};
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static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
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struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
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}
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static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit),
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BIT(sdm845_pdc_resets[idx].bit));
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}
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static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit), 0);
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}
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static const struct reset_control_ops qcom_pdc_reset_ops = {
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.assert = qcom_pdc_control_assert,
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.deassert = qcom_pdc_control_deassert,
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};
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static int qcom_pdc_reset_probe(struct platform_device *pdev)
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{
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struct qcom_pdc_reset_data *data;
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struct device *dev = &pdev->dev;
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void __iomem *base;
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struct resource *res;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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data->regmap = devm_regmap_init_mmio(dev, base,
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&sdm845_pdc_regmap_config);
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if (IS_ERR(data->regmap)) {
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dev_err(dev, "Unable to initialize regmap\n");
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return PTR_ERR(data->regmap);
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}
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.ops = &qcom_pdc_reset_ops;
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data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
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data->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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static const struct of_device_id qcom_pdc_reset_of_match[] = {
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{ .compatible = "qcom,sdm845-pdc-global" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
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static struct platform_driver qcom_pdc_reset_driver = {
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.probe = qcom_pdc_reset_probe,
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.driver = {
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.name = "qcom_pdc_reset",
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.of_match_table = qcom_pdc_reset_of_match,
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},
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};
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module_platform_driver(qcom_pdc_reset_driver);
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MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
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MODULE_LICENSE("GPL v2");