mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.

Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Acked-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>

authored by

Jiong Wang and committed by

Alexei Starovoitov 7 years ago ee94b90c 17f6c83f

+13 -4

6 changed files

expand all

arch

mips

include

asm

uasm.h

uapi

asm

inst.h

uasm-micromips.c

uasm-mips.c

uasm.c

net

ebpf_jit.c

arch/mips/include/asm/uasm.h

··· 157 157 Ip_u2u1s3(_sltiu); 158 158 Ip_u3u1u2(_sltu); 159 159 Ip_u2u1u3(_sra); 160 + Ip_u3u2u1(_srav); 160 161 Ip_u2u1u3(_srl); 161 162 Ip_u3u2u1(_srlv); 162 163 Ip_u3u1u2(_subu);

arch/mips/include/uapi/asm/inst.h

··· 371 371 mm_srl32_op = 0x040, 372 372 mm_srlv32_op = 0x050, 373 373 mm_sra_op = 0x080, 374 + mm_srav_op = 0x090, 374 375 mm_rotr_op = 0x0c0, 375 376 mm_lwxs_op = 0x118, 376 377 mm_addu32_op = 0x150,

arch/mips/mm/uasm-micromips.c

··· 104 104 [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, 105 105 [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD}, 106 106 [insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD}, 107 + [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD}, 107 108 [insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD}, 108 109 [insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD}, 109 110 [insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},

arch/mips/mm/uasm-mips.c

··· 171 171 [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 172 172 [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, 173 173 [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE}, 174 + [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD}, 174 175 [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE}, 175 176 [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, 176 177 [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},

+5 -4

arch/mips/mm/uasm.c

··· 61 61 insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor, 62 62 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, 63 63 insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv, 64 - insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl, 65 - insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, 66 - insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, 67 - insn_xori, insn_yield, 64 + insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav, 65 + insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, 66 + insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, 67 + insn_xor, insn_xori, insn_yield, 68 68 insn_invalid /* insn_invalid must be last */ 69 69 }; 70 70 ··· 353 353 I_u2u1s3(_sltiu) 354 354 I_u3u1u2(_sltu) 355 355 I_u2u1u3(_sra) 356 + I_u3u2u1(_srav) 356 357 I_u2u1u3(_srl) 357 358 I_u3u2u1(_srlv) 358 359 I_u2u1u3(_rotr)

arch/mips/net/ebpf_jit.c

··· 854 854 case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */ 855 855 case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */ 856 856 case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */ 857 + case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */ 857 858 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); 858 859 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); 859 860 if (src < 0 || dst < 0) ··· 913 912 break; 914 913 case BPF_RSH: 915 914 emit_instr(ctx, srlv, dst, dst, src); 915 + break; 916 + case BPF_ARSH: 917 + emit_instr(ctx, srav, dst, dst, src); 916 918 break; 917 919 default: 918 920 pr_err("ALU_REG NOT HANDLED\n");