mips: bpf: fix encoding bug for mm_srlv32_op

For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.

Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.

v1->v2:
- Keep mm_srlv32_op sorted by value.

Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras <[e-mail]>
Cc: Paul Burton <[e-mail]>
Cc: [e-mail]
Acked-by: Jakub Kicinski <[e-mail]>
Acked-by: Song Liu <[e-mail]>
Signed-off-by: Jiong Wang <[e-mail]>
Signed-off-by: Alexei Starovoitov <[e-mail]>

arch/mips/include/uapi/asm/inst.h

···
 	mm_ext_op = 0x02c,
 	mm_pool32axf_op = 0x03c,
 	mm_srl32_op = 0x040,
+	mm_srlv32_op = 0x050,
 	mm_sra_op = 0x080,
-	mm_srlv32_op = 0x090,
 	mm_rotr_op = 0x0c0,
 	mm_lwxs_op = 0x118,
 	mm_addu32_op = 0x150,