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linux
clk: mmp: Add Marvell PXA1908 MPMU driver
Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The
driver is incomplete, currently only supporting the fixed PLL1; dynamic
PLLs 2-4 and CPU/DDR/AXI clock support is missing.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-8-e050609b8d6c@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Duje Mihanović
and committed by
Stephen Boyd
ebac87cd
03437e85
+113
-1
+1
-1
drivers/clk/mmp/Makefile
+1
-1
drivers/clk/mmp/Makefile
···
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obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
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obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
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obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o
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obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o
+112
drivers/clk/mmp/clk-pxa1908-mpmu.c
+112
drivers/clk/mmp/clk-pxa1908-mpmu.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/units.h>
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#include <dt-bindings/clock/marvell,pxa1908.h>
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#include "clk.h"
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#define MPMU_UART_PLL 0x14
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#define MPMU_NR_CLKS 39
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struct pxa1908_clk_unit {
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struct mmp_clk_unit unit;
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void __iomem *base;
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};
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static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
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{PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
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{PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ},
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{PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ},
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{PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ},
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{PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ},
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{PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ},
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{PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ},
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};
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static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
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{PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0},
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{PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0},
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{PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0},
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{PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0},
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{PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0},
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{PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0},
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{PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0},
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{PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0},
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{PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0},
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{PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0},
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{PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0},
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{PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0},
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{PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0},
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};
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static struct u32_fract uart_factor_tbl[] = {
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{.numerator = 8125, .denominator = 1536}, /* 14.745MHz */
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};
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static struct mmp_clk_factor_masks uart_factor_masks = {
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.factor = 2,
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.num_mask = GENMASK(12, 0),
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.den_mask = GENMASK(12, 0),
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.num_shift = 16,
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.den_shift = 0,
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};
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static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit)
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{
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
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ARRAY_SIZE(fixed_rate_clks));
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mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
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ARRAY_SIZE(fixed_factor_clks));
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mmp_clk_register_factor("uart_pll", "pll1_d4",
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CLK_SET_RATE_PARENT,
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pxa_unit->base + MPMU_UART_PLL,
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&uart_factor_masks, uart_factor_tbl,
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ARRAY_SIZE(uart_factor_tbl), NULL);
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}
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static int pxa1908_mpmu_probe(struct platform_device *pdev)
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{
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struct pxa1908_clk_unit *pxa_unit;
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pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
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if (IS_ERR(pxa_unit))
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return PTR_ERR(pxa_unit);
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pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pxa_unit->base))
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return PTR_ERR(pxa_unit->base);
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mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, MPMU_NR_CLKS);
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pxa1908_pll_init(pxa_unit);
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return 0;
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}
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static const struct of_device_id pxa1908_mpmu_match_table[] = {
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{ .compatible = "marvell,pxa1908-mpmu" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pxa1908_mpmu_match_table);
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static struct platform_driver pxa1908_mpmu_driver = {
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.probe = pxa1908_mpmu_probe,
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.driver = {
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.name = "pxa1908-mpmu",
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.of_match_table = pxa1908_mpmu_match_table
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}
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};
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module_platform_driver(pxa1908_mpmu_driver);
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MODULE_AUTHOR("Duje Mihanović <duje.mihanovic@skole.hr>");
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MODULE_DESCRIPTION("Marvell PXA1908 MPMU Clock Driver");
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MODULE_LICENSE("GPL");