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kernel
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linux
clk: mmp: Add Marvell PXA1908 APMU driver
Add driver for the APMU controller block found on Marvell's PXA1908 SoC.
This driver is incomplete, lacking support for (at least) GPU, VPU, DSI
and CCIC (camera related) clocks.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-7-e050609b8d6c@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Duje Mihanović
and committed by
Stephen Boyd
03437e85
a89233db
+122
-1
+1
-1
drivers/clk/mmp/Makefile
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-1
drivers/clk/mmp/Makefile
···
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obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
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obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
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obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o
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obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o
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drivers/clk/mmp/clk-pxa1908-apmu.c
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drivers/clk/mmp/clk-pxa1908-apmu.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/marvell,pxa1908.h>
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#include "clk.h"
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#define APMU_CLK_GATE_CTRL 0x40
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#define APMU_CCIC1 0x24
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#define APMU_ISP 0x38
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#define APMU_DSI1 0x44
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#define APMU_DISP1 0x4c
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#define APMU_CCIC0 0x50
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#define APMU_SDH0 0x54
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#define APMU_SDH1 0x58
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#define APMU_USB 0x5c
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#define APMU_NF 0x60
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#define APMU_VPU 0xa4
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#define APMU_GC 0xcc
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#define APMU_SDH2 0xe0
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#define APMU_GC2D 0xf4
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#define APMU_TRACE 0x108
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#define APMU_DVC_DFC_DEBUG 0x140
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#define APMU_NR_CLKS 17
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struct pxa1908_clk_unit {
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struct mmp_clk_unit unit;
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void __iomem *base;
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};
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static DEFINE_SPINLOCK(pll1_lock);
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static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
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{PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
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{PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
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{PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
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{PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
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{PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
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};
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static DEFINE_SPINLOCK(sdh0_lock);
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static DEFINE_SPINLOCK(sdh1_lock);
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static DEFINE_SPINLOCK(sdh2_lock);
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static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
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static struct mmp_clk_mix_config sdh_mix_config = {
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.reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
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};
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static struct mmp_param_gate_clk apmu_gate_clks[] = {
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{PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
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{PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
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{PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
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{PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
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};
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static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
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{
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_general_gate_clks(unit, pll1_gate_clks,
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pxa_unit->base, ARRAY_SIZE(pll1_gate_clks));
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sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH0;
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mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
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ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
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&sdh_mix_config, &sdh0_lock);
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sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH1;
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mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
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ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
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&sdh_mix_config, &sdh1_lock);
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sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH2;
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mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
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ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
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&sdh_mix_config, &sdh2_lock);
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mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->base,
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ARRAY_SIZE(apmu_gate_clks));
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}
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static int pxa1908_apmu_probe(struct platform_device *pdev)
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{
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struct pxa1908_clk_unit *pxa_unit;
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pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
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if (IS_ERR(pxa_unit))
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return PTR_ERR(pxa_unit);
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pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pxa_unit->base))
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return PTR_ERR(pxa_unit->base);
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mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS);
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pxa1908_axi_periph_clk_init(pxa_unit);
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return 0;
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}
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static const struct of_device_id pxa1908_apmu_match_table[] = {
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{ .compatible = "marvell,pxa1908-apmu" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pxa1908_apmu_match_table);
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static struct platform_driver pxa1908_apmu_driver = {
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.probe = pxa1908_apmu_probe,
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.driver = {
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.name = "pxa1908-apmu",
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.of_match_table = pxa1908_apmu_match_table
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}
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};
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module_platform_driver(pxa1908_apmu_driver);
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MODULE_AUTHOR("Duje Mihanović <duje.mihanovic@skole.hr>");
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MODULE_DESCRIPTION("Marvell PXA1908 APMU Clock Driver");
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MODULE_LICENSE("GPL");