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linux
clk: sprd: Add macros for referencing parents without strings
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws and .parent_data, for clk drivers to specify parents without
name strings of clocks.
Also some macros were added for using these two items to reference
clock parents. Based on that to expand macros for sprd clocks:
- SPRD_*_DATA, take an array of struct clk_parent_data * as its parents
which should be a combination of .fw_name (devicetree clock-names),
.hw (pointers to a local struct clk_hw).
- SPRD_*_HW, take a local struct clk_hw pointer, instead of a string, as
its parent.
- SPRD_*_FW_NAME, take a string of clock-names decleared in the device
tree as the clock parent.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Chunyan Zhang
and committed by
Stephen Boyd
ea8ca310
be7ef655
+196
-55
+28
-11
drivers/clk/sprd/composite.h
+28
-11
drivers/clk/sprd/composite.h
···
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struct sprd_clk_common common;
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};
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-
#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, _dwidth, _flags) \
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+
#define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, _dwidth, \
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_flags, _fn) \
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struct sprd_comp _struct = { \
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.mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
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.div = _SPRD_DIV_CLK(_dshift, _dwidth), \
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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-
.hw.init = CLK_HW_INIT_PARENTS(_name, \
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-
_parent, \
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&sprd_comp_ops, \
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-
_flags), \
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.hw.init = _fn(_name, _parent, \
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&sprd_comp_ops, _flags), \
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} \
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}
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-
#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
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_mwidth, _dshift, _dwidth, _flags) \
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SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
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NULL, _mshift, _mwidth, \
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_dshift, _dwidth, _flags)
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+
#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, _dwidth, _flags) \
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SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, _dwidth, \
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_flags, CLK_HW_INIT_PARENTS)
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+
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#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
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_mwidth, _dshift, _dwidth, _flags) \
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SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
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_mshift, _mwidth, _dshift, _dwidth, _flags)
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+
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+
#define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, \
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_dwidth, _flags) \
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SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
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_mshift, _mwidth, _dshift, _dwidth, \
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_flags, CLK_HW_INIT_PARENTS_DATA)
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+
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#define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
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_mwidth, _dshift, _dwidth, _flags) \
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SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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_mshift, _mwidth, _dshift, _dwidth, \
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_flags)
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static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
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{
+14
-6
drivers/clk/sprd/div.h
+14
-6
drivers/clk/sprd/div.h
···
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struct sprd_clk_common common;
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};
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-
#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
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_shift, _width, _flags) \
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#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_shift, _width, _flags, _fn) \
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struct sprd_div _struct = { \
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.div = _SPRD_DIV_CLK(_shift, _width), \
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&sprd_div_ops, \
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-
_flags), \
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.hw.init = _fn(_name, _parent, \
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&sprd_div_ops, _flags), \
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} \
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}
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+
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#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
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_shift, _width, _flags) \
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SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_shift, _width, _flags, CLK_HW_INIT)
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+
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#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
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_shift, _width, _flags) \
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SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_shift, _width, _flags, CLK_HW_INIT_HW)
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static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
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{
+96
-13
drivers/clk/sprd/gate.h
+96
-13
drivers/clk/sprd/gate.h
···
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struct sprd_clk_common common;
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};
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-
#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
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#define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, _ops) \
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_gate_flags, _udelay, _ops, _fn) \
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struct sprd_gate _struct = { \
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.enable_mask = _enable_mask, \
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.sc_offset = _sc_offset, \
···
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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_ops, \
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_flags), \
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.hw.init = _fn(_name, _parent, \
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_ops, _flags), \
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} \
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}
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+
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#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, _ops) \
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SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, _ops, CLK_HW_INIT)
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#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
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_enable_mask, _flags, _gate_flags, _ops) \
···
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, 0, _ops)
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#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
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_enable_mask, _flags, _gate_flags) \
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SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
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_enable_mask, _flags, _gate_flags, \
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&sprd_gate_ops)
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-
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#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
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_enable_mask, _flags, _gate_flags) \
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SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
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_enable_mask, _flags, _gate_flags, \
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&sprd_sc_gate_ops)
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#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
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_enable_mask, _flags, _gate_flags) \
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SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
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_enable_mask, _flags, _gate_flags, \
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&sprd_gate_ops)
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+
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#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
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_enable_mask, _flags, _gate_flags, _udelay) \
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_enable_mask, _flags, _gate_flags, \
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_udelay) \
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SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, \
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&sprd_pll_sc_gate_ops)
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#define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, \
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_flags, _gate_flags, \
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_udelay, _ops) \
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SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, _ops, \
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CLK_HW_INIT_HW)
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#define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _ops) \
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SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, \
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_flags, _gate_flags, 0, _ops)
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#define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags) \
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SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, &sprd_sc_gate_ops)
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#define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \
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_enable_mask, _flags, _gate_flags) \
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SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, 0, \
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_enable_mask, _flags, _gate_flags, \
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&sprd_gate_ops)
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#define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay) \
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SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, \
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_flags, _gate_flags, _udelay, \
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&sprd_pll_sc_gate_ops)
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#define SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
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_reg, _sc_offset, \
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_enable_mask, _flags, \
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_gate_flags, _udelay, _ops) \
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SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay, _ops, \
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CLK_HW_INIT_FW_NAME)
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#define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _ops) \
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SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
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_reg, _sc_offset, \
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_enable_mask, _flags, \
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_gate_flags, 0, _ops)
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#define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags) \
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SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, &sprd_sc_gate_ops)
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#define SPRD_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
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_enable_mask, _flags, _gate_flags) \
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SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, 0, \
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_enable_mask, _flags, _gate_flags, \
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&sprd_gate_ops)
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#define SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
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_sc_offset, _enable_mask, _flags, \
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_gate_flags, _udelay) \
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SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
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_reg, _sc_offset, \
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_enable_mask, _flags, \
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_gate_flags, _udelay, \
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&sprd_pll_sc_gate_ops)
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static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
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{
+21
-7
drivers/clk/sprd/mux.h
+21
-7
drivers/clk/sprd/mux.h
···
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.table = _table, \
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}
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#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
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_reg, _shift, _width, \
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_flags) \
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#define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
40
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_reg, _shift, _width, _flags, _fn) \
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struct sprd_mux _struct = { \
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.mux = _SPRD_MUX_CLK(_shift, _width, _table), \
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parents, \
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&sprd_mux_ops, \
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_flags), \
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.hw.init = _fn(_name, _parents, \
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&sprd_mux_ops, _flags), \
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} \
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}
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#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
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_reg, _shift, _width, _flags) \
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SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
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_reg, _shift, _width, _flags, \
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CLK_HW_INIT_PARENTS)
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#define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
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_shift, _width, _flags) \
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SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
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_reg, _shift, _width, _flags)
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+
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#define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \
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_reg, _shift, _width, _flags) \
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SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
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_reg, _shift, _width, _flags, \
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CLK_HW_INIT_PARENTS_DATA)
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#define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \
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_shift, _width, _flags) \
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SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
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_reg, _shift, _width, _flags)
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static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)
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{
+37
-18
drivers/clk/sprd/pll.h
+37
-18
drivers/clk/sprd/pll.h
···
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struct sprd_clk_common common;
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};
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#define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
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_regs_num, _itable, _factors, \
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_udelay, _k1, _k2, _fflag, \
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_fvco, _fn) \
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struct sprd_pll _struct = { \
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.regs_num = _regs_num, \
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.itable = _itable, \
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.factors = _factors, \
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.udelay = _udelay, \
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.k1 = _k1, \
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.k2 = _k2, \
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.fflag = _fflag, \
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.fvco = _fvco, \
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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.hw.init = _fn(_name, _parent, \
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&sprd_pll_ops, 0),\
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}, \
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}
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#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
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_regs_num, _itable, _factors, \
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_udelay, _k1, _k2, _fflag, _fvco) \
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struct sprd_pll _struct = { \
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.regs_num = _regs_num, \
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.itable = _itable, \
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.factors = _factors, \
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.udelay = _udelay, \
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.k1 = _k1, \
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.k2 = _k2, \
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.fflag = _fflag, \
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.fvco = _fvco, \
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.common = { \
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.regmap = NULL, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&sprd_pll_ops, \
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0), \
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}, \
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}
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
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_itable, _factors, _udelay, _k1, _k2, \
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_fflag, _fvco, CLK_HW_INIT)
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#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
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_regs_num, _itable, _factors, \
···
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SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
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_regs_num, _itable, _factors, \
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_udelay, 1000, 1000, 0, 0)
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#define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
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_itable, _factors, _udelay, _k1, _k2, \
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_fflag, _fvco) \
102
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
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_itable, _factors, _udelay, _k1, _k2, \
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_fflag, _fvco, CLK_HW_INIT_FW_NAME)
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#define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \
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_factors, _udelay, _k1, _k2, _fflag, _fvco) \
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
109
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_itable, _factors, _udelay, _k1, _k2, \
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_fflag, _fvco, CLK_HW_INIT_HW)
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static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
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{