clk: sprd: Add dt-bindings include file for SC9863A

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

This file defines all SC9863A clock indexes, it should be included in the
device tree in which there's device using the clocks.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200304072730.9193-5-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Chunyan Zhang and committed by

Stephen Boyd 6 years ago be7ef655 eba8ba8a

+334

1 changed file

expand all

include

dt-bindings

clock

sprd,sc9863a-clk.h

+334

include/dt-bindings/clock/sprd,sc9863a-clk.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Unisoc SC9863A platform clocks 4 + * 5 + * Copyright (C) 2019, Unisoc Communications Inc. 6 + */ 7 + 8 + #ifndef _DT_BINDINGS_CLK_SC9863A_H_ 9 + #define _DT_BINDINGS_CLK_SC9863A_H_ 10 + 11 + #define CLK_MPLL0_GATE 0 12 + #define CLK_DPLL0_GATE 1 13 + #define CLK_LPLL_GATE 2 14 + #define CLK_GPLL_GATE 3 15 + #define CLK_DPLL1_GATE 4 16 + #define CLK_MPLL1_GATE 5 17 + #define CLK_MPLL2_GATE 6 18 + #define CLK_ISPPLL_GATE 7 19 + #define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1) 20 + 21 + #define CLK_AUDIO_GATE 0 22 + #define CLK_RPLL 1 23 + #define CLK_RPLL_390M 2 24 + #define CLK_RPLL_260M 3 25 + #define CLK_RPLL_195M 4 26 + #define CLK_RPLL_26M 5 27 + #define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1) 28 + 29 + #define CLK_TWPLL 0 30 + #define CLK_TWPLL_768M 1 31 + #define CLK_TWPLL_384M 2 32 + #define CLK_TWPLL_192M 3 33 + #define CLK_TWPLL_96M 4 34 + #define CLK_TWPLL_48M 5 35 + #define CLK_TWPLL_24M 6 36 + #define CLK_TWPLL_12M 7 37 + #define CLK_TWPLL_512M 8 38 + #define CLK_TWPLL_256M 9 39 + #define CLK_TWPLL_128M 10 40 + #define CLK_TWPLL_64M 11 41 + #define CLK_TWPLL_307M2 12 42 + #define CLK_TWPLL_219M4 13 43 + #define CLK_TWPLL_170M6 14 44 + #define CLK_TWPLL_153M6 15 45 + #define CLK_TWPLL_76M8 16 46 + #define CLK_TWPLL_51M2 17 47 + #define CLK_TWPLL_38M4 18 48 + #define CLK_TWPLL_19M2 19 49 + #define CLK_LPLL 20 50 + #define CLK_LPLL_409M6 21 51 + #define CLK_LPLL_245M76 22 52 + #define CLK_GPLL 23 53 + #define CLK_ISPPLL 24 54 + #define CLK_ISPPLL_468M 25 55 + #define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1) 56 + 57 + #define CLK_DPLL0 0 58 + #define CLK_DPLL1 1 59 + #define CLK_DPLL0_933M 2 60 + #define CLK_DPLL0_622M3 3 61 + #define CLK_DPLL0_400M 4 62 + #define CLK_DPLL0_266M7 5 63 + #define CLK_DPLL0_123M1 6 64 + #define CLK_DPLL0_50M 7 65 + #define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1) 66 + 67 + #define CLK_MPLL0 0 68 + #define CLK_MPLL1 1 69 + #define CLK_MPLL2 2 70 + #define CLK_MPLL2_675M 3 71 + #define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1) 72 + 73 + #define CLK_AP_APB 0 74 + #define CLK_AP_CE 1 75 + #define CLK_NANDC_ECC 2 76 + #define CLK_NANDC_26M 3 77 + #define CLK_EMMC_32K 4 78 + #define CLK_SDIO0_32K 5 79 + #define CLK_SDIO1_32K 6 80 + #define CLK_SDIO2_32K 7 81 + #define CLK_OTG_UTMI 8 82 + #define CLK_AP_UART0 9 83 + #define CLK_AP_UART1 10 84 + #define CLK_AP_UART2 11 85 + #define CLK_AP_UART3 12 86 + #define CLK_AP_UART4 13 87 + #define CLK_AP_I2C0 14 88 + #define CLK_AP_I2C1 15 89 + #define CLK_AP_I2C2 16 90 + #define CLK_AP_I2C3 17 91 + #define CLK_AP_I2C4 18 92 + #define CLK_AP_I2C5 19 93 + #define CLK_AP_I2C6 20 94 + #define CLK_AP_SPI0 21 95 + #define CLK_AP_SPI1 22 96 + #define CLK_AP_SPI2 23 97 + #define CLK_AP_SPI3 24 98 + #define CLK_AP_IIS0 25 99 + #define CLK_AP_IIS1 26 100 + #define CLK_AP_IIS2 27 101 + #define CLK_SIM0 28 102 + #define CLK_SIM0_32K 29 103 + #define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1) 104 + 105 + #define CLK_13M 0 106 + #define CLK_6M5 1 107 + #define CLK_4M3 2 108 + #define CLK_2M 3 109 + #define CLK_250K 4 110 + #define CLK_RCO_25M 5 111 + #define CLK_RCO_4M 6 112 + #define CLK_RCO_2M 7 113 + #define CLK_EMC 8 114 + #define CLK_AON_APB 9 115 + #define CLK_ADI 10 116 + #define CLK_AUX0 11 117 + #define CLK_AUX1 12 118 + #define CLK_AUX2 13 119 + #define CLK_PROBE 14 120 + #define CLK_PWM0 15 121 + #define CLK_PWM1 16 122 + #define CLK_PWM2 17 123 + #define CLK_AON_THM 18 124 + #define CLK_AUDIF 19 125 + #define CLK_CPU_DAP 20 126 + #define CLK_CPU_TS 21 127 + #define CLK_DJTAG_TCK 22 128 + #define CLK_EMC_REF 23 129 + #define CLK_CSSYS 24 130 + #define CLK_AON_PMU 25 131 + #define CLK_PMU_26M 26 132 + #define CLK_AON_TMR 27 133 + #define CLK_POWER_CPU 28 134 + #define CLK_AP_AXI 29 135 + #define CLK_SDIO0_2X 30 136 + #define CLK_SDIO1_2X 31 137 + #define CLK_SDIO2_2X 32 138 + #define CLK_EMMC_2X 33 139 + #define CLK_DPU 34 140 + #define CLK_DPU_DPI 35 141 + #define CLK_OTG_REF 36 142 + #define CLK_SDPHY_APB 37 143 + #define CLK_ALG_IO_APB 38 144 + #define CLK_GPU_CORE 39 145 + #define CLK_GPU_SOC 40 146 + #define CLK_MM_EMC 41 147 + #define CLK_MM_AHB 42 148 + #define CLK_BPC 43 149 + #define CLK_DCAM_IF 44 150 + #define CLK_ISP 45 151 + #define CLK_JPG 46 152 + #define CLK_CPP 47 153 + #define CLK_SENSOR0 48 154 + #define CLK_SENSOR1 49 155 + #define CLK_SENSOR2 50 156 + #define CLK_MM_VEMC 51 157 + #define CLK_MM_VAHB 52 158 + #define CLK_VSP 53 159 + #define CLK_CORE0 54 160 + #define CLK_CORE1 55 161 + #define CLK_CORE2 56 162 + #define CLK_CORE3 57 163 + #define CLK_CORE4 58 164 + #define CLK_CORE5 59 165 + #define CLK_CORE6 60 166 + #define CLK_CORE7 61 167 + #define CLK_SCU 62 168 + #define CLK_ACE 63 169 + #define CLK_AXI_PERIPH 64 170 + #define CLK_AXI_ACP 65 171 + #define CLK_ATB 66 172 + #define CLK_DEBUG_APB 67 173 + #define CLK_GIC 68 174 + #define CLK_PERIPH 69 175 + #define CLK_AON_CLK_NUM (CLK_VSP + 1) 176 + 177 + #define CLK_OTG_EB 0 178 + #define CLK_DMA_EB 1 179 + #define CLK_CE_EB 2 180 + #define CLK_NANDC_EB 3 181 + #define CLK_SDIO0_EB 4 182 + #define CLK_SDIO1_EB 5 183 + #define CLK_SDIO2_EB 6 184 + #define CLK_EMMC_EB 7 185 + #define CLK_EMMC_32K_EB 8 186 + #define CLK_SDIO0_32K_EB 9 187 + #define CLK_SDIO1_32K_EB 10 188 + #define CLK_SDIO2_32K_EB 11 189 + #define CLK_NANDC_26M_EB 12 190 + #define CLK_DMA_EB2 13 191 + #define CLK_CE_EB2 14 192 + #define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1) 193 + 194 + #define CLK_GPIO_EB 0 195 + #define CLK_PWM0_EB 1 196 + #define CLK_PWM1_EB 2 197 + #define CLK_PWM2_EB 3 198 + #define CLK_PWM3_EB 4 199 + #define CLK_KPD_EB 5 200 + #define CLK_AON_SYST_EB 6 201 + #define CLK_AP_SYST_EB 7 202 + #define CLK_AON_TMR_EB 8 203 + #define CLK_EFUSE_EB 9 204 + #define CLK_EIC_EB 10 205 + #define CLK_INTC_EB 11 206 + #define CLK_ADI_EB 12 207 + #define CLK_AUDIF_EB 13 208 + #define CLK_AUD_EB 14 209 + #define CLK_VBC_EB 15 210 + #define CLK_PIN_EB 16 211 + #define CLK_AP_WDG_EB 17 212 + #define CLK_MM_EB 18 213 + #define CLK_AON_APB_CKG_EB 19 214 + #define CLK_CA53_TS0_EB 20 215 + #define CLK_CA53_TS1_EB 21 216 + #define CLK_CS53_DAP_EB 22 217 + #define CLK_PMU_EB 23 218 + #define CLK_THM_EB 24 219 + #define CLK_AUX0_EB 25 220 + #define CLK_AUX1_EB 26 221 + #define CLK_AUX2_EB 27 222 + #define CLK_PROBE_EB 28 223 + #define CLK_EMC_REF_EB 29 224 + #define CLK_CA53_WDG_EB 30 225 + #define CLK_AP_TMR1_EB 31 226 + #define CLK_AP_TMR2_EB 32 227 + #define CLK_DISP_EMC_EB 33 228 + #define CLK_ZIP_EMC_EB 34 229 + #define CLK_GSP_EMC_EB 35 230 + #define CLK_MM_VSP_EB 36 231 + #define CLK_MDAR_EB 37 232 + #define CLK_RTC4M0_CAL_EB 38 233 + #define CLK_RTC4M1_CAL_EB 39 234 + #define CLK_DJTAG_EB 40 235 + #define CLK_MBOX_EB 41 236 + #define CLK_AON_DMA_EB 42 237 + #define CLK_AON_APB_DEF_EB 43 238 + #define CLK_CA5_TS0_EB 44 239 + #define CLK_DBG_EB 45 240 + #define CLK_DBG_EMC_EB 46 241 + #define CLK_CROSS_TRIG_EB 47 242 + #define CLK_SERDES_DPHY_EB 48 243 + #define CLK_ARCH_RTC_EB 49 244 + #define CLK_KPD_RTC_EB 50 245 + #define CLK_AON_SYST_RTC_EB 51 246 + #define CLK_AP_SYST_RTC_EB 52 247 + #define CLK_AON_TMR_RTC_EB 53 248 + #define CLK_AP_TMR0_RTC_EB 54 249 + #define CLK_EIC_RTC_EB 55 250 + #define CLK_EIC_RTCDV5_EB 56 251 + #define CLK_AP_WDG_RTC_EB 57 252 + #define CLK_CA53_WDG_RTC_EB 58 253 + #define CLK_THM_RTC_EB 59 254 + #define CLK_ATHMA_RTC_EB 60 255 + #define CLK_GTHMA_RTC_EB 61 256 + #define CLK_ATHMA_RTC_A_EB 62 257 + #define CLK_GTHMA_RTC_A_EB 63 258 + #define CLK_AP_TMR1_RTC_EB 64 259 + #define CLK_AP_TMR2_RTC_EB 65 260 + #define CLK_DXCO_LC_RTC_EB 66 261 + #define CLK_BB_CAL_RTC_EB 67 262 + #define CLK_GNU_EB 68 263 + #define CLK_DISP_EB 69 264 + #define CLK_MM_EMC_EB 70 265 + #define CLK_POWER_CPU_EB 71 266 + #define CLK_HW_I2C_EB 72 267 + #define CLK_MM_VSP_EMC_EB 73 268 + #define CLK_VSP_EB 74 269 + #define CLK_CSSYS_EB 75 270 + #define CLK_DMC_EB 76 271 + #define CLK_ROSC_EB 77 272 + #define CLK_S_D_CFG_EB 78 273 + #define CLK_S_D_REF_EB 79 274 + #define CLK_B_DMA_EB 80 275 + #define CLK_ANLG_EB 81 276 + #define CLK_ANLG_APB_EB 82 277 + #define CLK_BSMTMR_EB 83 278 + #define CLK_AP_AXI_EB 84 279 + #define CLK_AP_INTC0_EB 85 280 + #define CLK_AP_INTC1_EB 86 281 + #define CLK_AP_INTC2_EB 87 282 + #define CLK_AP_INTC3_EB 88 283 + #define CLK_AP_INTC4_EB 89 284 + #define CLK_AP_INTC5_EB 90 285 + #define CLK_SCC_EB 91 286 + #define CLK_DPHY_CFG_EB 92 287 + #define CLK_DPHY_REF_EB 93 288 + #define CLK_CPHY_CFG_EB 94 289 + #define CLK_OTG_REF_EB 95 290 + #define CLK_SERDES_EB 96 291 + #define CLK_AON_AP_EMC_EB 97 292 + #define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1) 293 + 294 + #define CLK_MAHB_CKG_EB 0 295 + #define CLK_MDCAM_EB 1 296 + #define CLK_MISP_EB 2 297 + #define CLK_MAHBCSI_EB 3 298 + #define CLK_MCSI_S_EB 4 299 + #define CLK_MCSI_T_EB 5 300 + #define CLK_DCAM_AXI_EB 6 301 + #define CLK_ISP_AXI_EB 7 302 + #define CLK_MCSI_EB 8 303 + #define CLK_MCSI_S_CKG_EB 9 304 + #define CLK_MCSI_T_CKG_EB 10 305 + #define CLK_SENSOR0_EB 11 306 + #define CLK_SENSOR1_EB 12 307 + #define CLK_SENSOR2_EB 13 308 + #define CLK_MCPHY_CFG_EB 14 309 + #define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) 310 + 311 + #define CLK_SIM0_EB 0 312 + #define CLK_IIS0_EB 1 313 + #define CLK_IIS1_EB 2 314 + #define CLK_IIS2_EB 3 315 + #define CLK_SPI0_EB 4 316 + #define CLK_SPI1_EB 5 317 + #define CLK_SPI2_EB 6 318 + #define CLK_I2C0_EB 7 319 + #define CLK_I2C1_EB 8 320 + #define CLK_I2C2_EB 9 321 + #define CLK_I2C3_EB 10 322 + #define CLK_I2C4_EB 11 323 + #define CLK_UART0_EB 12 324 + #define CLK_UART1_EB 13 325 + #define CLK_UART2_EB 14 326 + #define CLK_UART3_EB 15 327 + #define CLK_UART4_EB 16 328 + #define CLK_SIM0_32K_EB 17 329 + #define CLK_SPI3_EB 18 330 + #define CLK_I2C5_EB 19 331 + #define CLK_I2C6_EB 20 332 + #define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1) 333 + 334 + #endif /* _DT_BINDINGS_CLK_SC9863A_H_ */