tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: samsung: exynos4: Add divider clock id for memory bus frequency

This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling)
feature of the exynos memory bus.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

authored by

Chanwoo Choi and committed by
Sylwester Nawrocki e64fb42d 01e5200d

+11 -6
+5 -5
drivers/clk/samsung/clk-exynos4.c
··· 703 703 704 704 /* list of divider clocks supported in all exynos4 soc's */ 705 705 static struct samsung_div_clock exynos4_div_clks[] __initdata = { 706 - DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 706 + DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 707 707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 708 708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 709 709 CLKOUT_CMU_LEFTBUS, 8, 6), 710 710 711 - DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 711 + DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 712 712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 713 713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", 714 714 CLKOUT_CMU_RIGHTBUS, 8, 6), ··· 781 781 CLK_SET_RATE_PARENT, 0), 782 782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), 783 783 784 - DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 784 + DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 785 785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), 786 786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), 787 - DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 787 + DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 788 788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), 789 789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), 790 790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), ··· 829 829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 830 830 8, 3, CLK_GET_RATE_NOCACHE, 0), 831 831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 832 - DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 832 + DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 833 833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 834 834 }; 835 835
+6 -1
include/dt-bindings/clock/exynos4.h
··· 262 262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 263 263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 264 264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 265 + #define CLK_DIV_ACP 456 266 + #define CLK_DIV_DMC 457 267 + #define CLK_DIV_C2C 458 /* Exynos4x12 only */ 268 + #define CLK_DIV_GDL 459 269 + #define CLK_DIV_GDR 460 265 270 266 271 /* must be greater than maximal clock id */ 267 - #define CLK_NR_CLKS 456 272 + #define CLK_NR_CLKS 461 268 273 269 274 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */