tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code

This patch uses the samsung_cmu_register_one() to simplify code
for Exynos4415.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

authored by

Chanwoo Choi and committed by
Sylwester Nawrocki 01e5200d c913e1b3

+48 -168
+48 -168
drivers/clk/samsung/clk-exynos4415.c
··· 113 113 #define DIV_CPU0 0x14500 114 114 #define DIV_CPU1 0x14504 115 115 116 - enum exynos4415_plls { 117 - apll, epll, g3d_pll, isp_pll, disp_pll, 118 - nr_plls, 119 - }; 120 - 121 - static struct samsung_clk_provider *exynos4415_ctx; 122 - 123 - /* 124 - * Support for CMU save/restore across system suspends 125 - */ 126 - #ifdef CONFIG_PM_SLEEP 127 - static struct samsung_clk_reg_dump *exynos4415_clk_regs; 128 - 129 116 static unsigned long exynos4415_cmu_clk_regs[] __initdata = { 130 117 SRC_LEFTBUS, 131 118 DIV_LEFTBUS, ··· 205 218 DIV_CPU0, 206 219 DIV_CPU1, 207 220 }; 208 - 209 - static int exynos4415_clk_suspend(void) 210 - { 211 - samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs, 212 - ARRAY_SIZE(exynos4415_cmu_clk_regs)); 213 - 214 - return 0; 215 - } 216 - 217 - static void exynos4415_clk_resume(void) 218 - { 219 - samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs, 220 - ARRAY_SIZE(exynos4415_cmu_clk_regs)); 221 - } 222 - 223 - static struct syscore_ops exynos4415_clk_syscore_ops = { 224 - .suspend = exynos4415_clk_suspend, 225 - .resume = exynos4415_clk_resume, 226 - }; 227 - 228 - static void exynos4415_clk_sleep_init(void) 229 - { 230 - exynos4415_clk_regs = 231 - samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs, 232 - ARRAY_SIZE(exynos4415_cmu_clk_regs)); 233 - if (!exynos4415_clk_regs) { 234 - pr_warn("%s: Failed to allocate sleep save data\n", __func__); 235 - return; 236 - } 237 - 238 - register_syscore_ops(&exynos4415_clk_syscore_ops); 239 - } 240 - #else 241 - static inline void exynos4415_clk_sleep_init(void) { } 242 - #endif 243 221 244 222 /* list of all parent clock list */ 245 223 PNAME(mout_g3d_pllsrc_p) = { "fin_pll", }; ··· 911 959 { /* sentinel */ } 912 960 }; 913 961 914 - static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = { 915 - [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 916 - APLL_LOCK, APLL_CON0, NULL), 917 - [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 918 - EPLL_LOCK, EPLL_CON0, NULL), 919 - [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", 920 - "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL), 921 - [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll", 922 - ISP_PLL_LOCK, ISP_PLL_CON0, NULL), 923 - [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", 924 - "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL), 962 + static struct samsung_pll_clock exynos4415_plls[] __initdata = { 963 + PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 964 + APLL_LOCK, APLL_CON0, exynos4415_pll_rates), 965 + PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 966 + EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates), 967 + PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc", 968 + G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates), 969 + PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll", 970 + ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates), 971 + PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", 972 + "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates), 973 + }; 974 + 975 + static struct samsung_cmu_info cmu_info __initdata = { 976 + .pll_clks = exynos4415_plls, 977 + .nr_pll_clks = ARRAY_SIZE(exynos4415_plls), 978 + .mux_clks = exynos4415_mux_clks, 979 + .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks), 980 + .div_clks = exynos4415_div_clks, 981 + .nr_div_clks = ARRAY_SIZE(exynos4415_div_clks), 982 + .gate_clks = exynos4415_gate_clks, 983 + .nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks), 984 + .fixed_clks = exynos4415_fixed_rate_clks, 985 + .nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks), 986 + .fixed_factor_clks = exynos4415_fixed_factor_clks, 987 + .nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks), 988 + .nr_clk_ids = CLK_NR_CLKS, 989 + .clk_regs = exynos4415_cmu_clk_regs, 990 + .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs), 925 991 }; 926 992 927 993 static void __init exynos4415_cmu_init(struct device_node *np) 928 994 { 929 - void __iomem *reg_base; 930 - 931 - reg_base = of_iomap(np, 0); 932 - if (!reg_base) 933 - panic("%s: failed to map registers\n", __func__); 934 - 935 - exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 936 - if (!exynos4415_ctx) 937 - panic("%s: unable to allocate context.\n", __func__); 938 - 939 - exynos4415_plls[apll].rate_table = exynos4415_pll_rates; 940 - exynos4415_plls[epll].rate_table = exynos4415_epll_rates; 941 - exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates; 942 - exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates; 943 - exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates; 944 - 945 - samsung_clk_register_fixed_factor(exynos4415_ctx, 946 - exynos4415_fixed_factor_clks, 947 - ARRAY_SIZE(exynos4415_fixed_factor_clks)); 948 - samsung_clk_register_fixed_rate(exynos4415_ctx, 949 - exynos4415_fixed_rate_clks, 950 - ARRAY_SIZE(exynos4415_fixed_rate_clks)); 951 - 952 - samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls, 953 - ARRAY_SIZE(exynos4415_plls), reg_base); 954 - samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks, 955 - ARRAY_SIZE(exynos4415_mux_clks)); 956 - samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks, 957 - ARRAY_SIZE(exynos4415_div_clks)); 958 - samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks, 959 - ARRAY_SIZE(exynos4415_gate_clks)); 960 - 961 - exynos4415_clk_sleep_init(); 962 - 963 - samsung_clk_of_add_provider(np, exynos4415_ctx); 995 + samsung_cmu_register_one(np, &cmu_info); 964 996 } 965 997 CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init); 966 998 ··· 963 1027 #define SRC_DMC 0x300 964 1028 #define DIV_DMC1 0x504 965 1029 966 - enum exynos4415_dmc_plls { 967 - mpll, bpll, 968 - nr_dmc_plls, 969 - }; 970 - 971 - static struct samsung_clk_provider *exynos4415_dmc_ctx; 972 - 973 - #ifdef CONFIG_PM_SLEEP 974 - static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs; 975 - 976 1030 static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = { 977 1031 MPLL_LOCK, 978 1032 MPLL_CON0, ··· 975 1049 SRC_DMC, 976 1050 DIV_DMC1, 977 1051 }; 978 - 979 - static int exynos4415_dmc_clk_suspend(void) 980 - { 981 - samsung_clk_save(exynos4415_dmc_ctx->reg_base, 982 - exynos4415_dmc_clk_regs, 983 - ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs)); 984 - return 0; 985 - } 986 - 987 - static void exynos4415_dmc_clk_resume(void) 988 - { 989 - samsung_clk_restore(exynos4415_dmc_ctx->reg_base, 990 - exynos4415_dmc_clk_regs, 991 - ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs)); 992 - } 993 - 994 - static struct syscore_ops exynos4415_dmc_clk_syscore_ops = { 995 - .suspend = exynos4415_dmc_clk_suspend, 996 - .resume = exynos4415_dmc_clk_resume, 997 - }; 998 - 999 - static void exynos4415_dmc_clk_sleep_init(void) 1000 - { 1001 - exynos4415_dmc_clk_regs = 1002 - samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs, 1003 - ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs)); 1004 - if (!exynos4415_dmc_clk_regs) { 1005 - pr_warn("%s: Failed to allocate sleep save data\n", __func__); 1006 - return; 1007 - } 1008 - 1009 - register_syscore_ops(&exynos4415_dmc_clk_syscore_ops); 1010 - } 1011 - #else 1012 - static inline void exynos4415_dmc_clk_sleep_init(void) { } 1013 - #endif /* CONFIG_PM_SLEEP */ 1014 1052 1015 1053 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 1016 1054 PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; ··· 997 1107 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2), 998 1108 }; 999 1109 1000 - static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = { 1001 - [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", 1002 - MPLL_LOCK, MPLL_CON0, NULL), 1003 - [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", 1004 - BPLL_LOCK, BPLL_CON0, NULL), 1110 + static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = { 1111 + PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", 1112 + MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates), 1113 + PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", 1114 + BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates), 1115 + }; 1116 + 1117 + static struct samsung_cmu_info cmu_dmc_info __initdata = { 1118 + .pll_clks = exynos4415_dmc_plls, 1119 + .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls), 1120 + .mux_clks = exynos4415_dmc_mux_clks, 1121 + .nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks), 1122 + .div_clks = exynos4415_dmc_div_clks, 1123 + .nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks), 1124 + .nr_clk_ids = NR_CLKS_DMC, 1125 + .clk_regs = exynos4415_cmu_dmc_clk_regs, 1126 + .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs), 1005 1127 }; 1006 1128 1007 1129 static void __init exynos4415_cmu_dmc_init(struct device_node *np) 1008 1130 { 1009 - void __iomem *reg_base; 1010 - 1011 - reg_base = of_iomap(np, 0); 1012 - if (!reg_base) 1013 - panic("%s: failed to map registers\n", __func__); 1014 - 1015 - exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC); 1016 - if (!exynos4415_dmc_ctx) 1017 - panic("%s: unable to allocate context.\n", __func__); 1018 - 1019 - exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates; 1020 - exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates; 1021 - 1022 - samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls, 1023 - ARRAY_SIZE(exynos4415_dmc_plls), reg_base); 1024 - samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks, 1025 - ARRAY_SIZE(exynos4415_dmc_mux_clks)); 1026 - samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks, 1027 - ARRAY_SIZE(exynos4415_dmc_div_clks)); 1028 - 1029 - exynos4415_dmc_clk_sleep_init(); 1030 - 1031 - samsung_clk_of_add_provider(np, exynos4415_dmc_ctx); 1131 + samsung_cmu_register_one(np, &cmu_dmc_info); 1032 1132 } 1033 1133 CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc", 1034 1134 exynos4415_cmu_dmc_init);