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linux
MIPS: Loongson-3: Add RS780/SBX00 HPET support
CPUFreq driver need external timer, so add hpet at first.
In Loongson 3, only Core-0 can receive external interrupt. As a result,
timekeeping cannot absolutely use HPET timer. We use a hybrid solution:
Core-0 use HPET as its clock event device, but other cores still use
MIPS; clock source is global and doesn't need interrupt, so use HPET.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/8329/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Huacai Chen
and committed by
Ralf Baechle
e292ccde
89467e73
+350
-1
+73
arch/mips/include/asm/hpet.h
+73
arch/mips/include/asm/hpet.h
···
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#ifndef _ASM_HPET_H
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#define _ASM_HPET_H
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#ifdef CONFIG_RS780_HPET
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#define HPET_MMAP_SIZE 1024
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#define HPET_ID 0x000
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#define HPET_PERIOD 0x004
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#define HPET_CFG 0x010
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#define HPET_STATUS 0x020
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#define HPET_COUNTER 0x0f0
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#define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
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#define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
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#define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
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#define HPET_T0_IRS 0x001
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#define HPET_T1_IRS 0x002
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#define HPET_T3_IRS 0x004
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#define HPET_T0_CFG 0x100
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#define HPET_T0_CMP 0x108
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#define HPET_T0_ROUTE 0x110
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#define HPET_T1_CFG 0x120
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#define HPET_T1_CMP 0x128
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#define HPET_T1_ROUTE 0x130
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#define HPET_T2_CFG 0x140
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#define HPET_T2_CMP 0x148
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#define HPET_T2_ROUTE 0x150
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#define HPET_ID_REV 0x000000ff
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#define HPET_ID_NUMBER 0x00001f00
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#define HPET_ID_64BIT 0x00002000
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#define HPET_ID_LEGSUP 0x00008000
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#define HPET_ID_VENDOR 0xffff0000
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#define HPET_ID_NUMBER_SHIFT 8
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#define HPET_ID_VENDOR_SHIFT 16
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#define HPET_CFG_ENABLE 0x001
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#define HPET_CFG_LEGACY 0x002
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#define HPET_LEGACY_8254 2
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#define HPET_LEGACY_RTC 8
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#define HPET_TN_LEVEL 0x0002
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#define HPET_TN_ENABLE 0x0004
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#define HPET_TN_PERIODIC 0x0008
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#define HPET_TN_PERIODIC_CAP 0x0010
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#define HPET_TN_64BIT_CAP 0x0020
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#define HPET_TN_SETVAL 0x0040
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#define HPET_TN_32BIT 0x0100
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#define HPET_TN_ROUTE 0x3e00
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#define HPET_TN_FSB 0x4000
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#define HPET_TN_FSB_CAP 0x8000
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#define HPET_TN_ROUTE_SHIFT 9
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/* Max HPET Period is 10^8 femto sec as in HPET spec */
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#define HPET_MAX_PERIOD 100000000UL
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/*
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* Min HPET period is 10^5 femto sec just for safety. If it is less than this,
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* then 32 bit HPET counter wrapsaround in less than 0.5 sec.
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*/
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#define HPET_MIN_PERIOD 100000UL
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#define HPET_ADDR 0x20000
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#define HPET_MMIO_ADDR 0x90000e0000020000
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#define HPET_FREQ 14318780
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#define HPET_COMPARE_VAL ((HPET_FREQ + HZ / 2) / HZ)
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#define HPET_T0_IRQ 0
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extern void __init setup_hpet_timer(void);
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#endif /* CONFIG_RS780_HPET */
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#endif /* _ASM_HPET_H */
+12
arch/mips/loongson/Kconfig
+12
arch/mips/loongson/Kconfig
···
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If unsure, say Yes.
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config RS780_HPET
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bool "RS780/SBX00 HPET Timer"
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depends on LOONGSON_MACH3X
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select MIPS_EXTERNAL_TIMER
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help
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This option enables the hpet timer of AMD RS780/SBX00.
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If you want to enable the Loongson3 CPUFreq Driver, Please enable
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this option at first, otherwise, You will get wrong system time.
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If unsure, say Yes.
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config LOONGSON_SUSPEND
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bool
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default y
+5
arch/mips/loongson/common/time.c
+5
arch/mips/loongson/common/time.c
···
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*/
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#include <asm/mc146818-time.h>
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#include <asm/time.h>
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#include <asm/hpet.h>
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#include <loongson.h>
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#include <cs5536/cs5536_mfgpt.h>
···
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/* setup mips r4k timer */
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mips_hpt_frequency = cpu_clock_freq / 2;
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#ifdef CONFIG_RS780_HPET
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setup_hpet_timer();
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#else
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setup_mfgpt0_timer();
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#endif
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}
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void read_persistent_clock(struct timespec *ts)
+2
arch/mips/loongson/loongson-3/Makefile
+2
arch/mips/loongson/loongson-3/Makefile
+257
arch/mips/loongson/loongson-3/hpet.c
+257
arch/mips/loongson/loongson-3/hpet.c
···
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#define SMBUS_CFG_BASE (loongson_sysconf.ht_control_base + 0x0300a000)
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#define SMBUS_PCI_REG40 0x40
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#define SMBUS_PCI_REG64 0x64
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#define SMBUS_PCI_REGB4 0xb4
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static DEFINE_SPINLOCK(hpet_lock);
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DEFINE_PER_CPU(struct clock_event_device, hpet_clockevent_device);
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static unsigned int smbus_read(int offset)
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{
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return *(volatile unsigned int *)(SMBUS_CFG_BASE + offset);
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}
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static void smbus_write(int offset, int data)
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{
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*(volatile unsigned int *)(SMBUS_CFG_BASE + offset) = data;
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}
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static void smbus_enable(int offset, int bit)
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{
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unsigned int cfg = smbus_read(offset);
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cfg |= bit;
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smbus_write(offset, cfg);
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}
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static int hpet_read(int offset)
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{
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return *(volatile unsigned int *)(HPET_MMIO_ADDR + offset);
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}
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static void hpet_write(int offset, int data)
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{
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*(volatile unsigned int *)(HPET_MMIO_ADDR + offset) = data;
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}
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static void hpet_start_counter(void)
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{
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unsigned int cfg = hpet_read(HPET_CFG);
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cfg |= HPET_CFG_ENABLE;
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hpet_write(HPET_CFG, cfg);
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}
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static void hpet_stop_counter(void)
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{
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unsigned int cfg = hpet_read(HPET_CFG);
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cfg &= ~HPET_CFG_ENABLE;
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hpet_write(HPET_CFG, cfg);
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}
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static void hpet_reset_counter(void)
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{
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hpet_write(HPET_COUNTER, 0);
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hpet_write(HPET_COUNTER + 4, 0);
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}
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static void hpet_restart_counter(void)
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{
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hpet_stop_counter();
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hpet_reset_counter();
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hpet_start_counter();
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}
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static void hpet_enable_legacy_int(void)
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{
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/* Do nothing on Loongson-3 */
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}
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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int cfg = 0;
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spin_lock(&hpet_lock);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_info("set clock event to periodic mode!\n");
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/* stop counter */
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hpet_stop_counter();
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/* enables the timer0 to generate a periodic interrupt */
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cfg = hpet_read(HPET_T0_CFG);
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cfg &= ~HPET_TN_LEVEL;
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
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HPET_TN_SETVAL | HPET_TN_32BIT;
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hpet_write(HPET_T0_CFG, cfg);
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/* set the comparator */
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hpet_write(HPET_T0_CMP, HPET_COMPARE_VAL);
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udelay(1);
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hpet_write(HPET_T0_CMP, HPET_COMPARE_VAL);
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/* start counter */
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hpet_start_counter();
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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cfg = hpet_read(HPET_T0_CFG);
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cfg &= ~HPET_TN_ENABLE;
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hpet_write(HPET_T0_CFG, cfg);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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pr_info("set clock event to one shot mode!\n");
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cfg = hpet_read(HPET_T0_CFG);
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/* set timer0 type
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* 1 : periodic interrupt
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* 0 : non-periodic(oneshot) interrupt
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*/
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_write(HPET_T0_CFG, cfg);
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break;
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case CLOCK_EVT_MODE_RESUME:
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hpet_enable_legacy_int();
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break;
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}
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spin_unlock(&hpet_lock);
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}
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static int hpet_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned int cnt;
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int res;
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cnt = hpet_read(HPET_COUNTER);
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cnt += delta;
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hpet_write(HPET_T0_CMP, cnt);
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res = ((int)(hpet_read(HPET_COUNTER) - cnt) > 0) ? -ETIME : 0;
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return res;
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}
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static irqreturn_t hpet_irq_handler(int irq, void *data)
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{
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int is_irq;
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struct clock_event_device *cd;
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unsigned int cpu = smp_processor_id();
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is_irq = hpet_read(HPET_STATUS);
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if (is_irq & HPET_T0_IRS) {
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/* clear the TIMER0 irq status register */
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hpet_write(HPET_STATUS, HPET_T0_IRS);
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cd = &per_cpu(hpet_clockevent_device, cpu);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static struct irqaction hpet_irq = {
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.handler = hpet_irq_handler,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
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.name = "hpet",
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};
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/*
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* hpet address assignation and irq setting should be done in bios.
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* but pmon don't do this, we just setup here directly.
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* The operation under is normal. unfortunately, hpet_setup process
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* is before pci initialize.
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*
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* {
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* struct pci_dev *pdev;
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*
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* pdev = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
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* pci_write_config_word(pdev, SMBUS_PCI_REGB4, HPET_ADDR);
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*
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* ...
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* }
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*/
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static void hpet_setup(void)
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{
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/* set hpet base address */
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smbus_write(SMBUS_PCI_REGB4, HPET_ADDR);
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/* enable decodeing of access to HPET MMIO*/
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smbus_enable(SMBUS_PCI_REG40, (1 << 28));
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/* HPET irq enable */
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smbus_enable(SMBUS_PCI_REG64, (1 << 10));
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hpet_enable_legacy_int();
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}
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void __init setup_hpet_timer(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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hpet_setup();
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cd = &per_cpu(hpet_clockevent_device, cpu);
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cd->name = "hpet";
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cd->rating = 320;
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cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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cd->set_mode = hpet_set_mode;
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cd->set_next_event = hpet_next_event;
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cd->irq = HPET_T0_IRQ;
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cd->cpumask = cpumask_of(cpu);
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clockevent_set_clock(cd, HPET_FREQ);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = 5000;
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clockevents_register_device(cd);
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setup_irq(HPET_T0_IRQ, &hpet_irq);
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pr_info("hpet clock event device register\n");
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}
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static cycle_t hpet_read_counter(struct clocksource *cs)
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{
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return (cycle_t)hpet_read(HPET_COUNTER);
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}
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static void hpet_suspend(struct clocksource *cs)
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{
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}
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static void hpet_resume(struct clocksource *cs)
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{
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hpet_setup();
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hpet_restart_counter();
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}
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static struct clocksource csrc_hpet = {
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.name = "hpet",
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/* mips clocksource rating is less than 300, so hpet is better. */
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.rating = 300,
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.read = hpet_read_counter,
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.mask = CLOCKSOURCE_MASK(32),
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/* oneshot mode work normal with this flag */
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.suspend = hpet_suspend,
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.resume = hpet_resume,
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.mult = 0,
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.shift = 10,
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};
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int __init init_hpet_clocksource(void)
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{
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csrc_hpet.mult = clocksource_hz2mult(HPET_FREQ, csrc_hpet.shift);
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return clocksource_register_hz(&csrc_hpet, HPET_FREQ);
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}
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arch_initcall(init_hpet_clocksource);