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kernel
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linux
MIPS: Loongson-3: Add oprofile support
Loongson-3 has two groups of performance counters, they are 4 sub-
registers of CP0's REG25. This patch add oprofile support.
REG25, sel 0: Perf Control of group 0;
REG25, sel 1: Perf Counter of group 0;
REG25, sel 2: Perf Control of group 1;
REG25, sel 3: Perf Counter of group 1.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/8328/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Huacai Chen
and committed by
Ralf Baechle
89467e73
3adeb256
+225
+1
arch/mips/oprofile/Makefile
+1
arch/mips/oprofile/Makefile
+4
arch/mips/oprofile/common.c
+4
arch/mips/oprofile/common.c
···
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extern struct op_mips_model op_model_mipsxx_ops __weak;
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extern struct op_mips_model op_model_loongson2_ops __weak;
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extern struct op_mips_model op_model_loongson3_ops __weak;
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static struct op_mips_model *model;
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···
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case CPU_LOONGSON2:
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lmodel = &op_model_loongson2_ops;
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break;
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case CPU_LOONGSON3:
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lmodel = &op_model_loongson3_ops;
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break;
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};
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+220
arch/mips/oprofile/op_model_loongson3.c
+220
arch/mips/oprofile/op_model_loongson3.c
···
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/proc_fs.h>
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#include <linux/oprofile.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <asm/uaccess.h>
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#include <irq.h>
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#include <loongson.h>
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#include "op_impl.h"
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#define LOONGSON3_PERFCNT_OVERFLOW (1ULL << 63)
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#define LOONGSON3_PERFCTRL_EXL (1UL << 0)
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#define LOONGSON3_PERFCTRL_KERNEL (1UL << 1)
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#define LOONGSON3_PERFCTRL_SUPERVISOR (1UL << 2)
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#define LOONGSON3_PERFCTRL_USER (1UL << 3)
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#define LOONGSON3_PERFCTRL_ENABLE (1UL << 4)
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#define LOONGSON3_PERFCTRL_W (1UL << 30)
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#define LOONGSON3_PERFCTRL_M (1UL << 31)
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#define LOONGSON3_PERFCTRL_EVENT(idx, event) \
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(((event) & (idx ? 0x0f : 0x3f)) << 5)
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/* Loongson-3 PerfCount performance counter1 register */
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#define read_c0_perflo1() __read_64bit_c0_register($25, 0)
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#define write_c0_perflo1(val) __write_64bit_c0_register($25, 0, val)
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#define read_c0_perfhi1() __read_64bit_c0_register($25, 1)
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#define write_c0_perfhi1(val) __write_64bit_c0_register($25, 1, val)
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/* Loongson-3 PerfCount performance counter2 register */
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#define read_c0_perflo2() __read_64bit_c0_register($25, 2)
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#define write_c0_perflo2(val) __write_64bit_c0_register($25, 2, val)
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#define read_c0_perfhi2() __read_64bit_c0_register($25, 3)
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#define write_c0_perfhi2(val) __write_64bit_c0_register($25, 3, val)
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static int (*save_perf_irq)(void);
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static struct loongson3_register_config {
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unsigned int control1;
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unsigned int control2;
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unsigned long long reset_counter1;
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unsigned long long reset_counter2;
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int ctr1_enable, ctr2_enable;
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} reg;
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static void reset_counters(void *arg)
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{
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write_c0_perfhi1(0);
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write_c0_perfhi2(0);
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write_c0_perflo1(0xc0000000);
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write_c0_perflo2(0x40000000);
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}
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/* Compute all of the registers in preparation for enabling profiling. */
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static void loongson3_reg_setup(struct op_counter_config *ctr)
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{
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unsigned int control1 = 0;
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unsigned int control2 = 0;
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reg.reset_counter1 = 0;
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reg.reset_counter2 = 0;
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/* Compute the performance counter control word. */
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/* For now count kernel and user mode */
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if (ctr[0].enabled) {
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control1 |= LOONGSON3_PERFCTRL_EVENT(0, ctr[0].event) |
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LOONGSON3_PERFCTRL_ENABLE;
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if (ctr[0].kernel)
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control1 |= LOONGSON3_PERFCTRL_KERNEL;
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if (ctr[0].user)
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control1 |= LOONGSON3_PERFCTRL_USER;
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reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count;
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}
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if (ctr[1].enabled) {
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control2 |= LOONGSON3_PERFCTRL_EVENT(1, ctr[1].event) |
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LOONGSON3_PERFCTRL_ENABLE;
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if (ctr[1].kernel)
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control2 |= LOONGSON3_PERFCTRL_KERNEL;
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if (ctr[1].user)
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control2 |= LOONGSON3_PERFCTRL_USER;
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reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count;
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}
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if (ctr[0].enabled)
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control1 |= LOONGSON3_PERFCTRL_EXL;
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if (ctr[1].enabled)
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control2 |= LOONGSON3_PERFCTRL_EXL;
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reg.control1 = control1;
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reg.control2 = control2;
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reg.ctr1_enable = ctr[0].enabled;
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reg.ctr2_enable = ctr[1].enabled;
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void loongson3_cpu_setup(void *args)
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{
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uint64_t perfcount1, perfcount2;
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perfcount1 = reg.reset_counter1;
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perfcount2 = reg.reset_counter2;
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write_c0_perfhi1(perfcount1);
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write_c0_perfhi2(perfcount2);
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}
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static void loongson3_cpu_start(void *args)
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{
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/* Start all counters on current CPU */
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reg.control1 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M);
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reg.control2 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M);
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if (reg.ctr1_enable)
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write_c0_perflo1(reg.control1);
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if (reg.ctr2_enable)
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write_c0_perflo2(reg.control2);
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}
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static void loongson3_cpu_stop(void *args)
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{
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/* Stop all counters on current CPU */
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write_c0_perflo1(0xc0000000);
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write_c0_perflo2(0x40000000);
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memset(®, 0, sizeof(reg));
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}
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static int loongson3_perfcount_handler(void)
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{
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unsigned long flags;
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uint64_t counter1, counter2;
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uint32_t cause, handled = IRQ_NONE;
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struct pt_regs *regs = get_irq_regs();
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cause = read_c0_cause();
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if (!(cause & CAUSEF_PCI))
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return handled;
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counter1 = read_c0_perfhi1();
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counter2 = read_c0_perfhi2();
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local_irq_save(flags);
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if (counter1 & LOONGSON3_PERFCNT_OVERFLOW) {
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if (reg.ctr1_enable)
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oprofile_add_sample(regs, 0);
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counter1 = reg.reset_counter1;
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}
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if (counter2 & LOONGSON3_PERFCNT_OVERFLOW) {
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if (reg.ctr2_enable)
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oprofile_add_sample(regs, 1);
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counter2 = reg.reset_counter2;
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}
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local_irq_restore(flags);
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write_c0_perfhi1(counter1);
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write_c0_perfhi2(counter2);
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if (!(cause & CAUSEF_TI))
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handled = IRQ_HANDLED;
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return handled;
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}
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static int loongson3_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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switch (action) {
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case CPU_STARTING:
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case CPU_STARTING_FROZEN:
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write_c0_perflo1(reg.control1);
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write_c0_perflo2(reg.control2);
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break;
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case CPU_DYING:
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case CPU_DYING_FROZEN:
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write_c0_perflo1(0xc0000000);
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write_c0_perflo2(0x40000000);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block loongson3_notifier_block = {
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.notifier_call = loongson3_cpu_callback
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};
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static int __init loongson3_init(void)
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{
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on_each_cpu(reset_counters, NULL, 1);
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register_hotcpu_notifier(&loongson3_notifier_block);
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save_perf_irq = perf_irq;
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perf_irq = loongson3_perfcount_handler;
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return 0;
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}
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static void loongson3_exit(void)
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{
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on_each_cpu(reset_counters, NULL, 1);
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unregister_hotcpu_notifier(&loongson3_notifier_block);
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perf_irq = save_perf_irq;
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}
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struct op_mips_model op_model_loongson3_ops = {
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.reg_setup = loongson3_reg_setup,
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.cpu_setup = loongson3_cpu_setup,
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.init = loongson3_init,
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.exit = loongson3_exit,
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.cpu_start = loongson3_cpu_start,
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.cpu_stop = loongson3_cpu_stop,
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.cpu_type = "mips/loongson3",
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.num_counters = 2
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};