tjh.dev / kernel
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ARM: dts: r8a7740: use GIC_* defines

Use GIC_* defines for GIC interrupt cells in r8a7740 device tree.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Simon Horman e1e7b6fa 4d5746a3

+72 -71
+72 -71
arch/arm/boot/dts/r8a7740.dtsi
··· 11 11 /include/ "skeleton.dtsi" 12 12 13 13 #include <dt-bindings/clock/r8a7740-clock.h> 14 + #include <dt-bindings/interrupt-controller/arm-gic.h> 14 15 #include <dt-bindings/interrupt-controller/irq.h> 15 16 16 17 / { ··· 42 41 L2: cache-controller { 43 42 compatible = "arm,pl310-cache"; 44 43 reg = <0xf0100000 0x1000>; 45 - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 44 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 46 45 power-domains = <&pd_a3sm>; 47 46 arm,data-latency = <3 3 3>; 48 47 arm,tag-latency = <2 2 2>; ··· 59 58 60 59 pmu { 61 60 compatible = "arm,cortex-a9-pmu"; 62 - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 61 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 63 62 }; 64 63 65 64 ptm { ··· 70 69 cmt1: timer@e6138000 { 71 70 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 72 71 reg = <0xe6138000 0x170>; 73 - interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; 72 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 74 73 clocks = <&mstp3_clks R8A7740_CLK_CMT1>; 75 74 clock-names = "fck"; 76 75 power-domains = <&pd_c5>; ··· 90 89 <0xe6900020 1>, 91 90 <0xe6900040 1>, 92 91 <0xe6900060 1>; 93 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 94 - 0 149 IRQ_TYPE_LEVEL_HIGH 95 - 0 149 IRQ_TYPE_LEVEL_HIGH 96 - 0 149 IRQ_TYPE_LEVEL_HIGH 97 - 0 149 IRQ_TYPE_LEVEL_HIGH 98 - 0 149 IRQ_TYPE_LEVEL_HIGH 99 - 0 149 IRQ_TYPE_LEVEL_HIGH 100 - 0 149 IRQ_TYPE_LEVEL_HIGH>; 92 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 93 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 94 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 95 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 96 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 97 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 98 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 99 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 101 100 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 102 101 power-domains = <&pd_a4s>; 103 102 }; ··· 112 111 <0xe6900024 1>, 113 112 <0xe6900044 1>, 114 113 <0xe6900064 1>; 115 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 116 - 0 149 IRQ_TYPE_LEVEL_HIGH 117 - 0 149 IRQ_TYPE_LEVEL_HIGH 118 - 0 149 IRQ_TYPE_LEVEL_HIGH 119 - 0 149 IRQ_TYPE_LEVEL_HIGH 120 - 0 149 IRQ_TYPE_LEVEL_HIGH 121 - 0 149 IRQ_TYPE_LEVEL_HIGH 122 - 0 149 IRQ_TYPE_LEVEL_HIGH>; 114 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 115 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 116 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 117 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 118 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 119 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 120 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 121 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 123 122 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 124 123 power-domains = <&pd_a4s>; 125 124 }; ··· 134 133 <0xe6900028 1>, 135 134 <0xe6900048 1>, 136 135 <0xe6900068 1>; 137 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 138 - 0 149 IRQ_TYPE_LEVEL_HIGH 139 - 0 149 IRQ_TYPE_LEVEL_HIGH 140 - 0 149 IRQ_TYPE_LEVEL_HIGH 141 - 0 149 IRQ_TYPE_LEVEL_HIGH 142 - 0 149 IRQ_TYPE_LEVEL_HIGH 143 - 0 149 IRQ_TYPE_LEVEL_HIGH 144 - 0 149 IRQ_TYPE_LEVEL_HIGH>; 136 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 137 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 138 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 139 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 140 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 141 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 142 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 143 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 145 144 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 146 145 power-domains = <&pd_a4s>; 147 146 }; ··· 156 155 <0xe690002c 1>, 157 156 <0xe690004c 1>, 158 157 <0xe690006c 1>; 159 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 160 - 0 149 IRQ_TYPE_LEVEL_HIGH 161 - 0 149 IRQ_TYPE_LEVEL_HIGH 162 - 0 149 IRQ_TYPE_LEVEL_HIGH 163 - 0 149 IRQ_TYPE_LEVEL_HIGH 164 - 0 149 IRQ_TYPE_LEVEL_HIGH 165 - 0 149 IRQ_TYPE_LEVEL_HIGH 166 - 0 149 IRQ_TYPE_LEVEL_HIGH>; 158 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 159 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 160 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 161 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 162 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 163 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 164 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 165 + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 167 166 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 168 167 power-domains = <&pd_a4s>; 169 168 }; ··· 172 171 compatible = "renesas,gether-r8a7740"; 173 172 reg = <0xe9a00000 0x800>, 174 173 <0xe9a01800 0x800>; 175 - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 174 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 176 175 clocks = <&mstp3_clks R8A7740_CLK_GETHER>; 177 176 power-domains = <&pd_a4s>; 178 177 phy-mode = "mii"; ··· 186 185 #size-cells = <0>; 187 186 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 188 187 reg = <0xfff20000 0x425>; 189 - interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH 190 - 0 202 IRQ_TYPE_LEVEL_HIGH 191 - 0 203 IRQ_TYPE_LEVEL_HIGH 192 - 0 204 IRQ_TYPE_LEVEL_HIGH>; 188 + interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 189 + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 190 + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 191 + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 193 192 clocks = <&mstp1_clks R8A7740_CLK_IIC0>; 194 193 power-domains = <&pd_a4r>; 195 194 status = "disabled"; ··· 200 199 #size-cells = <0>; 201 200 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 202 201 reg = <0xe6c20000 0x425>; 203 - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH 204 - 0 71 IRQ_TYPE_LEVEL_HIGH 205 - 0 72 IRQ_TYPE_LEVEL_HIGH 206 - 0 73 IRQ_TYPE_LEVEL_HIGH>; 202 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 203 + GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH 204 + GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH 205 + GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 207 206 clocks = <&mstp3_clks R8A7740_CLK_IIC1>; 208 207 power-domains = <&pd_a3sp>; 209 208 status = "disabled"; ··· 212 211 scifa0: serial@e6c40000 { 213 212 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 214 213 reg = <0xe6c40000 0x100>; 215 - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 214 + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 216 215 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 217 216 clock-names = "sci_ick"; 218 217 power-domains = <&pd_a3sp>; ··· 222 221 scifa1: serial@e6c50000 { 223 222 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 224 223 reg = <0xe6c50000 0x100>; 225 - interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 224 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 226 225 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; 227 226 clock-names = "sci_ick"; 228 227 power-domains = <&pd_a3sp>; ··· 232 231 scifa2: serial@e6c60000 { 233 232 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 234 233 reg = <0xe6c60000 0x100>; 235 - interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 234 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 236 235 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; 237 236 clock-names = "sci_ick"; 238 237 power-domains = <&pd_a3sp>; ··· 242 241 scifa3: serial@e6c70000 { 243 242 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 244 243 reg = <0xe6c70000 0x100>; 245 - interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 244 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 246 245 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; 247 246 clock-names = "sci_ick"; 248 247 power-domains = <&pd_a3sp>; ··· 252 251 scifa4: serial@e6c80000 { 253 252 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 254 253 reg = <0xe6c80000 0x100>; 255 - interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 254 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 256 255 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; 257 256 clock-names = "sci_ick"; 258 257 power-domains = <&pd_a3sp>; ··· 262 261 scifa5: serial@e6cb0000 { 263 262 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 264 263 reg = <0xe6cb0000 0x100>; 265 - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 264 + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 266 265 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; 267 266 clock-names = "sci_ick"; 268 267 power-domains = <&pd_a3sp>; ··· 272 271 scifa6: serial@e6cc0000 { 273 272 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 274 273 reg = <0xe6cc0000 0x100>; 275 - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 274 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 276 275 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; 277 276 clock-names = "sci_ick"; 278 277 power-domains = <&pd_a3sp>; ··· 282 281 scifa7: serial@e6cd0000 { 283 282 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 284 283 reg = <0xe6cd0000 0x100>; 285 - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 284 + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 286 285 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; 287 286 clock-names = "sci_ick"; 288 287 power-domains = <&pd_a3sp>; ··· 292 291 scifb: serial@e6c30000 { 293 292 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 294 293 reg = <0xe6c30000 0x100>; 295 - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 294 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 296 295 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 297 296 clock-names = "sci_ick"; 298 297 power-domains = <&pd_a3sp>; ··· 330 329 mmcif0: mmc@e6bd0000 { 331 330 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; 332 331 reg = <0xe6bd0000 0x100>; 333 - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 334 - 0 57 IRQ_TYPE_LEVEL_HIGH>; 332 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 333 + GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 335 334 clocks = <&mstp3_clks R8A7740_CLK_MMC>; 336 335 power-domains = <&pd_a3sp>; 337 336 status = "disabled"; ··· 340 339 sdhi0: sd@e6850000 { 341 340 compatible = "renesas,sdhi-r8a7740"; 342 341 reg = <0xe6850000 0x100>; 343 - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 344 - 0 118 IRQ_TYPE_LEVEL_HIGH 345 - 0 119 IRQ_TYPE_LEVEL_HIGH>; 342 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 343 + GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 344 + GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 346 345 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; 347 346 power-domains = <&pd_a3sp>; 348 347 cap-sd-highspeed; ··· 353 352 sdhi1: sd@e6860000 { 354 353 compatible = "renesas,sdhi-r8a7740"; 355 354 reg = <0xe6860000 0x100>; 356 - interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 357 - 0 122 IRQ_TYPE_LEVEL_HIGH 358 - 0 123 IRQ_TYPE_LEVEL_HIGH>; 355 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 356 + GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 357 + GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 359 358 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; 360 359 power-domains = <&pd_a3sp>; 361 360 cap-sd-highspeed; ··· 366 365 sdhi2: sd@e6870000 { 367 366 compatible = "renesas,sdhi-r8a7740"; 368 367 reg = <0xe6870000 0x100>; 369 - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 370 - 0 126 IRQ_TYPE_LEVEL_HIGH 371 - 0 127 IRQ_TYPE_LEVEL_HIGH>; 368 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 369 + GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 370 + GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 372 371 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; 373 372 power-domains = <&pd_a3sp>; 374 373 cap-sd-highspeed; ··· 380 379 #sound-dai-cells = <1>; 381 380 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 382 381 reg = <0xfe1f0000 0x400>; 383 - interrupts = <0 9 0x4>; 382 + interrupts = <GIC_SPI 9 0x4>; 384 383 clocks = <&mstp3_clks R8A7740_CLK_FSI>; 385 384 power-domains = <&pd_a4mp>; 386 385 status = "disabled"; ··· 389 388 tmu0: timer@fff80000 { 390 389 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 391 390 reg = <0xfff80000 0x2c>; 392 - interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, 393 - <0 199 IRQ_TYPE_LEVEL_HIGH>, 394 - <0 200 IRQ_TYPE_LEVEL_HIGH>; 391 + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 392 + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 393 + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 395 394 clocks = <&mstp1_clks R8A7740_CLK_TMU0>; 396 395 clock-names = "fck"; 397 396 power-domains = <&pd_a4r>; ··· 404 403 tmu1: timer@fff90000 { 405 404 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 406 405 reg = <0xfff90000 0x2c>; 407 - interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, 408 - <0 171 IRQ_TYPE_LEVEL_HIGH>, 409 - <0 172 IRQ_TYPE_LEVEL_HIGH>; 406 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 407 + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 408 + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 410 409 clocks = <&mstp1_clks R8A7740_CLK_TMU1>; 411 410 clock-names = "fck"; 412 411 power-domains = <&pd_a4r>;