tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ARM: dts: r8a73a4: use GIC_* defines

Use GIC_* defines for GIC interrupt cells in r8a73a4 device tree.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

Simon Horman 4d5746a3 493b4da7

+106 -106
+106 -106
arch/arm/boot/dts/r8a73a4.dtsi
··· 39 39 40 40 timer { 41 41 compatible = "arm,armv7-timer"; 42 - interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43 - <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 44 - <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 - <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 42 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 44 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 46 46 }; 47 47 48 48 dbsc1: memory-controller@e6790000 { ··· 69 69 dma0: dma-controller@e6700020 { 70 70 compatible = "renesas,shdma-r8a73a4"; 71 71 reg = <0 0xe6700020 0 0x89e0>; 72 - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 73 - 0 200 IRQ_TYPE_LEVEL_HIGH 74 - 0 201 IRQ_TYPE_LEVEL_HIGH 75 - 0 202 IRQ_TYPE_LEVEL_HIGH 76 - 0 203 IRQ_TYPE_LEVEL_HIGH 77 - 0 204 IRQ_TYPE_LEVEL_HIGH 78 - 0 205 IRQ_TYPE_LEVEL_HIGH 79 - 0 206 IRQ_TYPE_LEVEL_HIGH 80 - 0 207 IRQ_TYPE_LEVEL_HIGH 81 - 0 208 IRQ_TYPE_LEVEL_HIGH 82 - 0 209 IRQ_TYPE_LEVEL_HIGH 83 - 0 210 IRQ_TYPE_LEVEL_HIGH 84 - 0 211 IRQ_TYPE_LEVEL_HIGH 85 - 0 212 IRQ_TYPE_LEVEL_HIGH 86 - 0 213 IRQ_TYPE_LEVEL_HIGH 87 - 0 214 IRQ_TYPE_LEVEL_HIGH 88 - 0 215 IRQ_TYPE_LEVEL_HIGH 89 - 0 216 IRQ_TYPE_LEVEL_HIGH 90 - 0 217 IRQ_TYPE_LEVEL_HIGH 91 - 0 218 IRQ_TYPE_LEVEL_HIGH 92 - 0 219 IRQ_TYPE_LEVEL_HIGH>; 72 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 73 + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 74 + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 75 + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 76 + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 77 + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 78 + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 79 + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 80 + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 81 + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 82 + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 83 + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 84 + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 85 + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 86 + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 87 + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 88 + GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 89 + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 90 + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 91 + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 92 + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 93 93 interrupt-names = "error", 94 94 "ch0", "ch1", "ch2", "ch3", 95 95 "ch4", "ch5", "ch6", "ch7", ··· 106 106 #size-cells = <0>; 107 107 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 108 108 reg = <0 0xe60b0000 0 0x428>; 109 - interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 109 + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 110 110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 111 111 power-domains = <&pd_a3sp>; 112 112 ··· 116 116 cmt1: timer@e6130000 { 117 117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; 118 118 reg = <0 0xe6130000 0 0x1004>; 119 - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 119 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 120 120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 121 121 clock-names = "fck"; 122 122 power-domains = <&pd_c5>; ··· 131 131 #interrupt-cells = <2>; 132 132 interrupt-controller; 133 133 reg = <0 0xe61c0000 0 0x200>; 134 - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 135 - <0 1 IRQ_TYPE_LEVEL_HIGH>, 136 - <0 2 IRQ_TYPE_LEVEL_HIGH>, 137 - <0 3 IRQ_TYPE_LEVEL_HIGH>, 138 - <0 4 IRQ_TYPE_LEVEL_HIGH>, 139 - <0 5 IRQ_TYPE_LEVEL_HIGH>, 140 - <0 6 IRQ_TYPE_LEVEL_HIGH>, 141 - <0 7 IRQ_TYPE_LEVEL_HIGH>, 142 - <0 8 IRQ_TYPE_LEVEL_HIGH>, 143 - <0 9 IRQ_TYPE_LEVEL_HIGH>, 144 - <0 10 IRQ_TYPE_LEVEL_HIGH>, 145 - <0 11 IRQ_TYPE_LEVEL_HIGH>, 146 - <0 12 IRQ_TYPE_LEVEL_HIGH>, 147 - <0 13 IRQ_TYPE_LEVEL_HIGH>, 148 - <0 14 IRQ_TYPE_LEVEL_HIGH>, 149 - <0 15 IRQ_TYPE_LEVEL_HIGH>, 150 - <0 16 IRQ_TYPE_LEVEL_HIGH>, 151 - <0 17 IRQ_TYPE_LEVEL_HIGH>, 152 - <0 18 IRQ_TYPE_LEVEL_HIGH>, 153 - <0 19 IRQ_TYPE_LEVEL_HIGH>, 154 - <0 20 IRQ_TYPE_LEVEL_HIGH>, 155 - <0 21 IRQ_TYPE_LEVEL_HIGH>, 156 - <0 22 IRQ_TYPE_LEVEL_HIGH>, 157 - <0 23 IRQ_TYPE_LEVEL_HIGH>, 158 - <0 24 IRQ_TYPE_LEVEL_HIGH>, 159 - <0 25 IRQ_TYPE_LEVEL_HIGH>, 160 - <0 26 IRQ_TYPE_LEVEL_HIGH>, 161 - <0 27 IRQ_TYPE_LEVEL_HIGH>, 162 - <0 28 IRQ_TYPE_LEVEL_HIGH>, 163 - <0 29 IRQ_TYPE_LEVEL_HIGH>, 164 - <0 30 IRQ_TYPE_LEVEL_HIGH>, 165 - <0 31 IRQ_TYPE_LEVEL_HIGH>; 134 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 166 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 167 167 power-domains = <&pd_c4>; 168 168 }; ··· 172 172 #interrupt-cells = <2>; 173 173 interrupt-controller; 174 174 reg = <0 0xe61c0200 0 0x200>; 175 - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 176 - <0 33 IRQ_TYPE_LEVEL_HIGH>, 177 - <0 34 IRQ_TYPE_LEVEL_HIGH>, 178 - <0 35 IRQ_TYPE_LEVEL_HIGH>, 179 - <0 36 IRQ_TYPE_LEVEL_HIGH>, 180 - <0 37 IRQ_TYPE_LEVEL_HIGH>, 181 - <0 38 IRQ_TYPE_LEVEL_HIGH>, 182 - <0 39 IRQ_TYPE_LEVEL_HIGH>, 183 - <0 40 IRQ_TYPE_LEVEL_HIGH>, 184 - <0 41 IRQ_TYPE_LEVEL_HIGH>, 185 - <0 42 IRQ_TYPE_LEVEL_HIGH>, 186 - <0 43 IRQ_TYPE_LEVEL_HIGH>, 187 - <0 44 IRQ_TYPE_LEVEL_HIGH>, 188 - <0 45 IRQ_TYPE_LEVEL_HIGH>, 189 - <0 46 IRQ_TYPE_LEVEL_HIGH>, 190 - <0 47 IRQ_TYPE_LEVEL_HIGH>, 191 - <0 48 IRQ_TYPE_LEVEL_HIGH>, 192 - <0 49 IRQ_TYPE_LEVEL_HIGH>, 193 - <0 50 IRQ_TYPE_LEVEL_HIGH>, 194 - <0 51 IRQ_TYPE_LEVEL_HIGH>, 195 - <0 52 IRQ_TYPE_LEVEL_HIGH>, 196 - <0 53 IRQ_TYPE_LEVEL_HIGH>, 197 - <0 54 IRQ_TYPE_LEVEL_HIGH>, 198 - <0 55 IRQ_TYPE_LEVEL_HIGH>, 199 - <0 56 IRQ_TYPE_LEVEL_HIGH>, 200 - <0 57 IRQ_TYPE_LEVEL_HIGH>; 175 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 176 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 177 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 178 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 179 + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 180 + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 181 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 182 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 183 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 184 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 185 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 186 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 187 + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 188 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 189 + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 190 + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 191 + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 192 + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 193 + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 194 + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 195 + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 196 + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 197 + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 198 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 199 + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 200 + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 201 201 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 202 202 power-domains = <&pd_c4>; 203 203 }; ··· 237 237 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 238 238 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 239 239 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 240 - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 240 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 241 241 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 242 242 power-domains = <&pd_c5>; 243 243 }; ··· 247 247 #size-cells = <0>; 248 248 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 249 249 reg = <0 0xe6500000 0 0x428>; 250 - interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 250 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 251 251 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 252 252 power-domains = <&pd_a3sp>; 253 253 status = "disabled"; ··· 258 258 #size-cells = <0>; 259 259 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 260 260 reg = <0 0xe6510000 0 0x428>; 261 - interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 261 + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 262 262 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 263 263 power-domains = <&pd_a3sp>; 264 264 status = "disabled"; ··· 269 269 #size-cells = <0>; 270 270 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 271 271 reg = <0 0xe6520000 0 0x428>; 272 - interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 272 + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 273 273 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 274 274 power-domains = <&pd_a3sp>; 275 275 status = "disabled"; ··· 280 280 #size-cells = <0>; 281 281 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 282 282 reg = <0 0xe6530000 0 0x428>; 283 - interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 283 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 284 284 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 285 285 power-domains = <&pd_a3sp>; 286 286 status = "disabled"; ··· 291 291 #size-cells = <0>; 292 292 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 293 293 reg = <0 0xe6540000 0 0x428>; 294 - interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 294 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 295 295 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 296 296 power-domains = <&pd_a3sp>; 297 297 status = "disabled"; ··· 302 302 #size-cells = <0>; 303 303 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 304 304 reg = <0 0xe6550000 0 0x428>; 305 - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 305 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 306 306 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 307 307 power-domains = <&pd_a3sp>; 308 308 status = "disabled"; ··· 313 313 #size-cells = <0>; 314 314 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 315 315 reg = <0 0xe6560000 0 0x428>; 316 - interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 316 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 317 317 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 318 318 power-domains = <&pd_a3sp>; 319 319 status = "disabled"; ··· 324 324 #size-cells = <0>; 325 325 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 326 326 reg = <0 0xe6570000 0 0x428>; 327 - interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 327 + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 328 328 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 329 329 power-domains = <&pd_a3sp>; 330 330 status = "disabled"; ··· 333 333 scifb0: serial@e6c20000 { 334 334 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 335 335 reg = <0 0xe6c20000 0 0x100>; 336 - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 336 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 337 337 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 338 338 clock-names = "sci_ick"; 339 339 power-domains = <&pd_a3sp>; ··· 343 343 scifb1: serial@e6c30000 { 344 344 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 345 345 reg = <0 0xe6c30000 0 0x100>; 346 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 346 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 347 347 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 348 348 clock-names = "sci_ick"; 349 349 power-domains = <&pd_a3sp>; ··· 353 353 scifa0: serial@e6c40000 { 354 354 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 355 355 reg = <0 0xe6c40000 0 0x100>; 356 - interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 356 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 357 357 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 358 358 clock-names = "sci_ick"; 359 359 power-domains = <&pd_a3sp>; ··· 363 363 scifa1: serial@e6c50000 { 364 364 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 365 365 reg = <0 0xe6c50000 0 0x100>; 366 - interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 366 + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 367 367 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 368 368 clock-names = "sci_ick"; 369 369 power-domains = <&pd_a3sp>; ··· 373 373 scifb2: serial@e6ce0000 { 374 374 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 375 375 reg = <0 0xe6ce0000 0 0x100>; 376 - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 376 + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 377 377 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 378 378 clock-names = "sci_ick"; 379 379 power-domains = <&pd_a3sp>; ··· 383 383 scifb3: serial@e6cf0000 { 384 384 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 385 385 reg = <0 0xe6cf0000 0 0x100>; 386 - interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 386 + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 387 387 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 388 388 clock-names = "sci_ick"; 389 389 power-domains = <&pd_c4>; ··· 393 393 sdhi0: sd@ee100000 { 394 394 compatible = "renesas,sdhi-r8a73a4"; 395 395 reg = <0 0xee100000 0 0x100>; 396 - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 396 + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 397 397 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 398 398 power-domains = <&pd_a3sp>; 399 399 cap-sd-highspeed; ··· 403 403 sdhi1: sd@ee120000 { 404 404 compatible = "renesas,sdhi-r8a73a4"; 405 405 reg = <0 0xee120000 0 0x100>; 406 - interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 406 + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 407 407 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 408 408 power-domains = <&pd_a3sp>; 409 409 cap-sd-highspeed; ··· 413 413 sdhi2: sd@ee140000 { 414 414 compatible = "renesas,sdhi-r8a73a4"; 415 415 reg = <0 0xee140000 0 0x100>; 416 - interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 416 + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 417 417 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 418 418 power-domains = <&pd_a3sp>; 419 419 cap-sd-highspeed; ··· 423 423 mmcif0: mmc@ee200000 { 424 424 compatible = "renesas,sh-mmcif"; 425 425 reg = <0 0xee200000 0 0x80>; 426 - interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 426 + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 427 427 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 428 428 power-domains = <&pd_a3sp>; 429 429 reg-io-width = <4>; ··· 433 433 mmcif1: mmc@ee220000 { 434 434 compatible = "renesas,sh-mmcif"; 435 435 reg = <0 0xee220000 0 0x80>; 436 - interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 436 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 437 437 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 438 438 power-domains = <&pd_a3sp>; 439 439 reg-io-width = <4>; ··· 449 449 <0 0xf1002000 0 0x1000>, 450 450 <0 0xf1004000 0 0x2000>, 451 451 <0 0xf1006000 0 0x2000>; 452 - interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 452 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 453 453 }; 454 454 455 455 bsc: bus@fec10000 {