···295 unsigned long diff, parent_rate, calc_rate; \296 int i; \297 \0298 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \299 bm_busy = BM_CLKCTRL_##dr##_BUSY; \300 \301 if (clk->parent == &ref_xtal_clk) { \302+ parent_rate = clk_get_rate(clk->parent); \303 div = DIV_ROUND_UP(parent_rate, rate); \304 if (clk == &cpu_clk) { \305 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \···309 if (div == 0 || div > div_max) \310 return -EINVAL; \311 } else { \312+ /* \313+ * hack alert: this block modifies clk->parent, too, \314+ * so the base to use it the grand parent. \315+ */ \316+ parent_rate = clk_get_rate(clk->parent->parent); \317 rate >>= PARENT_RATE_SHIFT; \318 parent_rate >>= PARENT_RATE_SHIFT; \319 diff = parent_rate; \
+7
arch/arm/plat-mxc/gpio.c
···295 return 0;296}297000000298int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)299{300 int i, j;···317 __raw_writel(~0, port[i].base + GPIO_ISR);318 for (j = port[i].virtual_irq_start;319 j < port[i].virtual_irq_start + 32; j++) {0320 irq_set_chip_and_handler(j, &gpio_irq_chip,321 handle_level_irq);322 set_irq_flags(j, IRQF_VALID);
···295 return 0;296}297298+/*299+ * This lock class tells lockdep that GPIO irqs are in a different300+ * category than their parents, so it won't report false recursion.301+ */302+static struct lock_class_key gpio_lock_class;303+304int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)305{306 int i, j;···311 __raw_writel(~0, port[i].base + GPIO_ISR);312 for (j = port[i].virtual_irq_start;313 j < port[i].virtual_irq_start + 32; j++) {314+ irq_set_lockdep_class(j, &gpio_lock_class);315 irq_set_chip_and_handler(j, &gpio_irq_chip,316 handle_level_irq);317 set_irq_flags(j, IRQF_VALID);