···295295 unsigned long diff, parent_rate, calc_rate; \296296 int i; \297297 \298298- parent_rate = clk_get_rate(clk->parent); \299298 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \300299 bm_busy = BM_CLKCTRL_##dr##_BUSY; \301300 \302301 if (clk->parent == &ref_xtal_clk) { \302302+ parent_rate = clk_get_rate(clk->parent); \303303 div = DIV_ROUND_UP(parent_rate, rate); \304304 if (clk == &cpu_clk) { \305305 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \···309309 if (div == 0 || div > div_max) \310310 return -EINVAL; \311311 } else { \312312+ /* \313313+ * hack alert: this block modifies clk->parent, too, \314314+ * so the base to use it the grand parent. \315315+ */ \316316+ parent_rate = clk_get_rate(clk->parent->parent); \312317 rate >>= PARENT_RATE_SHIFT; \313318 parent_rate >>= PARENT_RATE_SHIFT; \314319 diff = parent_rate; \
+7
arch/arm/plat-mxc/gpio.c
···295295 return 0;296296}297297298298+/*299299+ * This lock class tells lockdep that GPIO irqs are in a different300300+ * category than their parents, so it won't report false recursion.301301+ */302302+static struct lock_class_key gpio_lock_class;303303+298304int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)299305{300306 int i, j;···317311 __raw_writel(~0, port[i].base + GPIO_ISR);318312 for (j = port[i].virtual_irq_start;319313 j < port[i].virtual_irq_start + 32; j++) {314314+ irq_set_lockdep_class(j, &gpio_lock_class);320315 irq_set_chip_and_handler(j, &gpio_irq_chip,321316 handle_level_irq);322317 set_irq_flags(j, IRQF_VALID);