···337337 uint scc_tcrc; /* Internal */338338} sccp_t;339339340340+/* Function code bits.341341+*/342342+#define SCC_EB ((u_char) 0x10) /* Set big endian byte order */343343+#define SCC_GBL ((u_char) 0x20) /* Snooping enabled */344344+340345/* CPM Ethernet through SCC1.341346 */342347typedef struct scc_enet {
+3-3
drivers/net/Kconfig
···822822 will be called smc-ultra32.823823824824config BFIN_MAC825825- tristate "Blackfin 527/536/537 on-chip mac support"826826- depends on NET_ETHERNET && (BF527 || BF537 || BF536)825825+ tristate "Blackfin on-chip MAC support"826826+ depends on NET_ETHERNET && (BF526 || BF527 || BF536 || BF537)827827 select CRC32828828 select MII829829 select PHYLIB830830 select BFIN_MAC_USE_L1 if DMA_UNCACHED_NONE831831 help832832- This is the driver for blackfin on-chip mac device. Say Y if you want it832832+ This is the driver for Blackfin on-chip mac device. Say Y if you want it833833 compiled into the kernel. This driver is also available as a module834834 ( = code which can be inserted in and removed from the running kernel835835 whenever you want). The module will be called bfin_mac.
···792792 int r;793793 int err;794794795795+ /* to initialize the fep->cur_rx,... */796796+ /* not doing this, will cause a crash in fs_enet_rx_napi */797797+ fs_init_bds(fep->ndev);798798+795799 if (fep->fpi->use_napi)796800 napi_enable(&fep->napi);797801···11691165#ifdef CONFIG_FS_ENET_HAS_SCC11701166 {11711167 .compatible = "fsl,cpm1-scc-enet",11681168+ .data = (void *)&fs_scc_ops,11691169+ },11701170+ {11711171+ .compatible = "fsl,cpm2-scc-enet",11721172 .data = (void *)&fs_scc_ops,11731173 },11741174#endif
+7-1
drivers/net/fs_enet/mac-scc.c
···4747#include "fs_enet.h"48484949/*************************************************/5050-5150#if defined(CONFIG_CPM1)5251/* for a 8xx __raw_xxx's are sufficient */5352#define __fs_out32(addr, x) __raw_writel(x, addr)···6162#define __fs_out16(addr, x) out_be16(addr, x)6263#define __fs_in32(addr) in_be32(addr)6364#define __fs_in16(addr) in_be16(addr)6565+#define __fs_out8(addr, x) out_8(addr, x)6666+#define __fs_in8(addr) in_8(addr)6467#endif65686669/* write, read, set bits, clear bits */···263262264263 /* Initialize function code registers for big-endian.265264 */265265+#ifndef CONFIG_NOT_COHERENT_CACHE266266+ W8(ep, sen_genscc.scc_rfcr, SCC_EB | SCC_GBL);267267+ W8(ep, sen_genscc.scc_tfcr, SCC_EB | SCC_GBL);268268+#else266269 W8(ep, sen_genscc.scc_rfcr, SCC_EB);267270 W8(ep, sen_genscc.scc_tfcr, SCC_EB);271271+#endif268272269273 /* Set maximum bytes per receive buffer.270274 * This appears to be an Ethernet frame size, not the buffer
+18-4
drivers/net/gianfar.c
···105105106106static int gfar_enet_open(struct net_device *dev);107107static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);108108+static void gfar_reset_task(struct work_struct *work);108109static void gfar_timeout(struct net_device *dev);109110static int gfar_close(struct net_device *dev);110111struct sk_buff *gfar_new_skb(struct net_device *dev);···210209 spin_lock_init(&priv->txlock);211210 spin_lock_init(&priv->rxlock);212211 spin_lock_init(&priv->bflock);212212+ INIT_WORK(&priv->reset_task, gfar_reset_task);213213214214 platform_set_drvdata(pdev, dev);215215···1214121212151213 napi_disable(&priv->napi);1216121412151215+ cancel_work_sync(&priv->reset_task);12171216 stop_gfar(dev);1218121712191218 /* Disconnect from the PHY */···13291326 return 0;13301327}1331132813321332-/* gfar_timeout gets called when a packet has not been13291329+/* gfar_reset_task gets scheduled when a packet has not been13331330 * transmitted after a set amount of time.13341331 * For now, assume that clearing out all the structures, and13351335- * starting over will fix the problem. */13361336-static void gfar_timeout(struct net_device *dev)13321332+ * starting over will fix the problem.13331333+ */13341334+static void gfar_reset_task(struct work_struct *work)13371335{13381338- dev->stats.tx_errors++;13361336+ struct gfar_private *priv = container_of(work, struct gfar_private,13371337+ reset_task);13381338+ struct net_device *dev = priv->dev;1339133913401340 if (dev->flags & IFF_UP) {13411341 stop_gfar(dev);···13461340 }1347134113481342 netif_tx_schedule_all(dev);13431343+}13441344+13451345+static void gfar_timeout(struct net_device *dev)13461346+{13471347+ struct gfar_private *priv = netdev_priv(dev);13481348+13491349+ dev->stats.tx_errors++;13501350+ schedule_work(&priv->reset_task);13491351}1350135213511353/* Interrupt Handler for Transmit complete */
···8787 case E1000_DEV_ID_82576:8888 case E1000_DEV_ID_82576_FIBER:8989 case E1000_DEV_ID_82576_SERDES:9090- case E1000_DEV_ID_82576_QUAD_COPPER:9190 mac->type = e1000_82576;9291 break;9392 default:
···373373 regs_buff[12] = rd32(E1000_EECD);374374375375 /* Interrupt */376376- regs_buff[13] = rd32(E1000_EICR);376376+ /* Reading EICS for EICR because they read the377377+ * same but EICS does not clear on read */378378+ regs_buff[13] = rd32(E1000_EICS);377379 regs_buff[14] = rd32(E1000_EICS);378380 regs_buff[15] = rd32(E1000_EIMS);379381 regs_buff[16] = rd32(E1000_EIMC);380382 regs_buff[17] = rd32(E1000_EIAC);381383 regs_buff[18] = rd32(E1000_EIAM);382382- regs_buff[19] = rd32(E1000_ICR);384384+ /* Reading ICS for ICR because they read the385385+ * same but ICS does not clear on read */386386+ regs_buff[19] = rd32(E1000_ICS);383387 regs_buff[20] = rd32(E1000_ICS);384388 regs_buff[21] = rd32(E1000_IMS);385389 regs_buff[22] = rd32(E1000_IMC);···17441740 case E1000_DEV_ID_82576_SERDES:17451741 /* Wake events not supported on port B */17461742 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {17471747- wol->supported = 0;17481748- break;17491749- }17501750- /* return success for non excluded adapter ports */17511751- retval = 0;17521752- break;17531753- case E1000_DEV_ID_82576_QUAD_COPPER:17541754- /* quad port adapters only support WoL on port A */17551755- if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {17561743 wol->supported = 0;17571744 break;17581745 }
+11-14
drivers/net/igb/igb_main.c
···6161 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },6262 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },6363 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },6464- { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },6564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },6665 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },6766 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },···520521 adapter->msix_entries,521522 numvecs);522523 if (err == 0)523523- return;524524+ goto out;524525525526 igb_reset_interrupt_capability(adapter);526527···530531 adapter->num_tx_queues = 1;531532 if (!pci_enable_msi(adapter->pdev))532533 adapter->flags |= IGB_FLAG_HAS_MSI;533533-534534+out:534535 /* Notify the stack of the (possibly) reduced Tx Queue count. */535536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;536537 return;···12151216 * regardless of eeprom setting */12161217 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)12171218 adapter->eeprom_wol = 0;12181218- break;12191219- case E1000_DEV_ID_82576_QUAD_COPPER:12201220- /* if quad port adapter, disable WoL on all but port A */12211221- if (global_quad_port_a != 0)12221222- adapter->eeprom_wol = 0;12231223- else12241224- adapter->flags |= IGB_FLAG_QUAD_PORT_A;12251225- /* Reset for multiple quad port adapters */12261226- if (++global_quad_port_a == 4)12271227- global_quad_port_a = 0;12281219 break;12291220 }12301221···22792290 struct igb_ring *tx_ring = adapter->tx_ring;22802291 struct e1000_mac_info *mac = &adapter->hw.mac;22812292 u32 link;22932293+ u32 eics = 0;22822294 s32 ret_val;22952295+ int i;2283229622842297 if ((netif_carrier_ok(netdev)) &&22852298 (rd32(E1000_STATUS) & E1000_STATUS_LU))···23832392 }2384239323852394 /* Cause software interrupt to ensure rx ring is cleaned */23862386- wr32(E1000_ICS, E1000_ICS_RXDMT0);23952395+ if (adapter->msix_entries) {23962396+ for (i = 0; i < adapter->num_rx_queues; i++)23972397+ eics |= adapter->rx_ring[i].eims_value;23982398+ wr32(E1000_EICS, eics);23992399+ } else {24002400+ wr32(E1000_ICS, E1000_ICS_RXDMT0);24012401+ }2387240223882403 /* Force detection of hung controller every watchdog period */23892404 tx_ring->detect_tx_hung = true;
···14121412 }14131413 /* How far in the ccw chain have we processed? */14141414 if ((channel->state != LCS_CH_STATE_INIT) &&14151415- (irb->scsw.cmd.fctl & SCSW_FCTL_START_FUNC)) {14151415+ (irb->scsw.cmd.fctl & SCSW_FCTL_START_FUNC) &&14161416+ (irb->scsw.cmd.cpa != 0)) {14161417 index = (struct ccw1 *) __va((addr_t) irb->scsw.cmd.cpa)14171418 - channel->ccws;14181419 if ((irb->scsw.cmd.actl & SCSW_ACTL_SUSPENDED) ||
···30243024 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,30253025 int offset)30263026{30273027- int length = skb->len;30273027+ int length = skb->len - offset;30283028 int length_here;30293029 int element;30303030 char *data;