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ARM: clk-imx6sl: refine clock tree for SSI

Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

authored by

Shengjiu Wang and committed by
Shawn Guo dbaf381f dc4805c2

+14 -4
+10 -3
arch/arm/mach-imx/clk-imx6sl.c
··· 95 95 { } 96 96 }; 97 97 98 + static unsigned int share_count_ssi1; 99 + static unsigned int share_count_ssi2; 100 + static unsigned int share_count_ssi3; 101 + 98 102 static struct clk *clks[IMX6SL_CLK_END]; 99 103 static struct clk_onecell_data clk_data; 100 104 static void __iomem *ccm_base; ··· 396 392 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); 397 393 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 398 394 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); 399 - clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 400 - clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 401 - clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); 395 + clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); 396 + clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); 397 + clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); 398 + clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); 399 + clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); 400 + clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); 402 401 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); 403 402 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); 404 403 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
+4 -1
include/dt-bindings/clock/imx6sl-clock.h
··· 171 171 #define IMX6SL_PLL5_BYPASS 158 172 172 #define IMX6SL_PLL6_BYPASS 159 173 173 #define IMX6SL_PLL7_BYPASS 160 174 - #define IMX6SL_CLK_END 161 174 + #define IMX6SL_CLK_SSI1_IPG 161 175 + #define IMX6SL_CLK_SSI2_IPG 162 176 + #define IMX6SL_CLK_SSI3_IPG 163 177 + #define IMX6SL_CLK_END 164 175 178 176 179 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */