Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver

Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

Shawn Guo dc4805c2 db7c0659

-37
-37
arch/arm/mach-imx/clk-pllv3.c
··· 23 23 #define PLL_DENOM_OFFSET 0x20 24 24 25 25 #define BM_PLL_POWER (0x1 << 12) 26 - #define BM_PLL_ENABLE (0x1 << 13) 27 - #define BM_PLL_BYPASS (0x1 << 16) 28 26 #define BM_PLL_LOCK (0x1 << 31) 29 27 30 28 /** ··· 82 84 if (ret) 83 85 return ret; 84 86 85 - val = readl_relaxed(pll->base); 86 - val &= ~BM_PLL_BYPASS; 87 - writel_relaxed(val, pll->base); 88 - 89 87 return 0; 90 88 } 91 89 ··· 91 97 u32 val; 92 98 93 99 val = readl_relaxed(pll->base); 94 - val |= BM_PLL_BYPASS; 95 100 if (pll->powerup_set) 96 101 val &= ~BM_PLL_POWER; 97 102 else 98 103 val |= BM_PLL_POWER; 99 - writel_relaxed(val, pll->base); 100 - } 101 - 102 - static int clk_pllv3_enable(struct clk_hw *hw) 103 - { 104 - struct clk_pllv3 *pll = to_clk_pllv3(hw); 105 - u32 val; 106 - 107 - val = readl_relaxed(pll->base); 108 - val |= BM_PLL_ENABLE; 109 - writel_relaxed(val, pll->base); 110 - 111 - return 0; 112 - } 113 - 114 - static void clk_pllv3_disable(struct clk_hw *hw) 115 - { 116 - struct clk_pllv3 *pll = to_clk_pllv3(hw); 117 - u32 val; 118 - 119 - val = readl_relaxed(pll->base); 120 - val &= ~BM_PLL_ENABLE; 121 104 writel_relaxed(val, pll->base); 122 105 } 123 106 ··· 140 169 static const struct clk_ops clk_pllv3_ops = { 141 170 .prepare = clk_pllv3_prepare, 142 171 .unprepare = clk_pllv3_unprepare, 143 - .enable = clk_pllv3_enable, 144 - .disable = clk_pllv3_disable, 145 172 .recalc_rate = clk_pllv3_recalc_rate, 146 173 .round_rate = clk_pllv3_round_rate, 147 174 .set_rate = clk_pllv3_set_rate, ··· 194 225 static const struct clk_ops clk_pllv3_sys_ops = { 195 226 .prepare = clk_pllv3_prepare, 196 227 .unprepare = clk_pllv3_unprepare, 197 - .enable = clk_pllv3_enable, 198 - .disable = clk_pllv3_disable, 199 228 .recalc_rate = clk_pllv3_sys_recalc_rate, 200 229 .round_rate = clk_pllv3_sys_round_rate, 201 230 .set_rate = clk_pllv3_sys_set_rate, ··· 266 299 static const struct clk_ops clk_pllv3_av_ops = { 267 300 .prepare = clk_pllv3_prepare, 268 301 .unprepare = clk_pllv3_unprepare, 269 - .enable = clk_pllv3_enable, 270 - .disable = clk_pllv3_disable, 271 302 .recalc_rate = clk_pllv3_av_recalc_rate, 272 303 .round_rate = clk_pllv3_av_round_rate, 273 304 .set_rate = clk_pllv3_av_set_rate, ··· 280 315 static const struct clk_ops clk_pllv3_enet_ops = { 281 316 .prepare = clk_pllv3_prepare, 282 317 .unprepare = clk_pllv3_unprepare, 283 - .enable = clk_pllv3_enable, 284 - .disable = clk_pllv3_disable, 285 318 .recalc_rate = clk_pllv3_enet_recalc_rate, 286 319 }; 287 320