tjh.dev / kernel
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drm/panel: nt36672e: Break some CMDS into helper functions

Break select page cmds and reload cmds into helper functions.

Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20240710084715.1119935-4-yangcong5@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240710084715.1119935-4-yangcong5@huaqin.corp-partner.google.com

authored by

Cong Yang and committed by
Neil Armstrong d969b31a 3c8d2d5d

+44 -25
+44 -25
drivers/gpu/drm/panel/panel-novatek-nt36672e.c
··· 44 44 const struct panel_desc *desc; 45 45 }; 46 46 47 + #define NT36672E_DCS_SWITCH_PAGE 0xff 48 + 49 + #define nt36672e_switch_page(ctx, page) \ 50 + mipi_dsi_dcs_write_seq_multi(ctx, NT36672E_DCS_SWITCH_PAGE, (page)) 51 + 52 + static void nt36672e_enable_reload_cmds(struct mipi_dsi_multi_context *ctx) 53 + { 54 + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 55 + } 56 + 47 57 static inline struct nt36672e_panel *to_nt36672e_panel(struct drm_panel *panel) 48 58 { 49 59 return container_of(panel, struct nt36672e_panel, panel); ··· 61 51 62 52 static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) 63 53 { 64 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); 65 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 54 + nt36672e_switch_page(ctx, 0x10); 55 + nt36672e_enable_reload_cmds(ctx); 66 56 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00); 67 57 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); 68 58 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xaa, 0x02, 69 59 0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7); 70 - 71 60 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x1b, 0xa0); 72 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); 73 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 61 + 62 + nt36672e_switch_page(ctx, 0x20); 63 + nt36672e_enable_reload_cmds(ctx); 74 64 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66); 75 65 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40); 76 66 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38); ··· 86 76 mipi_dsi_dcs_write_seq_multi(ctx, 0xf7, 0x54); 87 77 mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x64); 88 78 mipi_dsi_dcs_write_seq_multi(ctx, 0xf9, 0x54); 89 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x24); 90 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 79 + 80 + nt36672e_switch_page(ctx, 0x24); 81 + nt36672e_enable_reload_cmds(ctx); 91 82 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0f); 92 83 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x0c); 93 84 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x1d); ··· 150 139 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x00); 151 140 mipi_dsi_dcs_write_seq_multi(ctx, 0xd9, 0x80); 152 141 mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x02); 153 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x25); 154 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 142 + 143 + nt36672e_switch_page(ctx, 0x25); 144 + nt36672e_enable_reload_cmds(ctx); 155 145 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x22); 156 146 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0xe4); 157 147 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x40); ··· 176 164 mipi_dsi_dcs_write_seq_multi(ctx, 0xd7, 0x80); 177 165 mipi_dsi_dcs_write_seq_multi(ctx, 0xef, 0x20); 178 166 mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x84); 179 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x26); 180 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 167 + 168 + nt36672e_switch_page(ctx, 0x26); 169 + nt36672e_enable_reload_cmds(ctx); 181 170 mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x0f); 182 171 mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x01); 183 172 mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x03); ··· 198 185 mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x00); 199 186 mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x00); 200 187 mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x00); 201 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x27); 202 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 188 + 189 + nt36672e_switch_page(ctx, 0x27); 190 + nt36672e_enable_reload_cmds(ctx); 203 191 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x68); 204 192 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x81); 205 193 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x6a); ··· 229 215 mipi_dsi_dcs_write_seq_multi(ctx, 0xe6, 0xd3); 230 216 mipi_dsi_dcs_write_seq_multi(ctx, 0xeb, 0x03); 231 217 mipi_dsi_dcs_write_seq_multi(ctx, 0xec, 0x28); 232 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2a); 233 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 218 + 219 + nt36672e_switch_page(ctx, 0x2a); 220 + nt36672e_enable_reload_cmds(ctx); 234 221 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x91); 235 222 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x20); 236 223 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x50); ··· 275 260 mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x7d); 276 261 mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x7d); 277 262 mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x7d); 278 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); 279 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 263 + 264 + nt36672e_switch_page(ctx, 0x20); 265 + nt36672e_enable_reload_cmds(ctx); 280 266 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 281 267 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); 282 268 mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, ··· 302 286 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 303 287 mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 304 288 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 305 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x21); 306 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 289 + 290 + nt36672e_switch_page(ctx, 0x21); 291 + nt36672e_enable_reload_cmds(ctx); 307 292 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 308 293 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); 309 294 mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, ··· 329 312 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 330 313 mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 331 314 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 332 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2c); 333 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 315 + 316 + nt36672e_switch_page(ctx, 0x2c); 317 + nt36672e_enable_reload_cmds(ctx); 334 318 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x1f); 335 319 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x1f); 336 320 mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x03); ··· 345 327 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x0f); 346 328 mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x0f); 347 329 mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x0f); 348 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xf0); 349 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 330 + 331 + nt36672e_switch_page(ctx, 0xf0); 332 + nt36672e_enable_reload_cmds(ctx); 350 333 mipi_dsi_dcs_write_seq_multi(ctx, 0x5a, 0x00); 351 334 352 - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); 353 - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 335 + nt36672e_switch_page(ctx, 0x10); 336 + nt36672e_enable_reload_cmds(ctx); 354 337 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xff); 355 338 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x24); 356 339 mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x01);