Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: dts: Add support for the cpuimx27 board from Eukrea and its baseboard

This patch adds support for the cpuimx27 board from Eukrea and its
baseboard. This change is intended to further remove non-DT support
for this board.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

authored by

Alexander Shiyan and committed by
Shawn Guo
d8cae888 d2daa2f7

+571
+1
arch/arm/boot/dts/Makefile
··· 161 161 imx25-pdk.dtb \ 162 162 imx27-apf27.dtb \ 163 163 imx27-apf27dev.dtb \ 164 + imx27-eukrea-mbimxsd27-baseboard.dtb \ 164 165 imx27-pdk.dtb \ 165 166 imx27-phytec-phycore-rdk.dtb \ 166 167 imx27-phytec-phycard-s-rdk.dtb \
+296
arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
··· 1 + /* 2 + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3 + * 4 + * The code contained herein is licensed under the GNU General Public 5 + * License. You may obtain a copy of the GNU General Public License 6 + * Version 2 or later at the following locations: 7 + * 8 + * http://www.opensource.org/licenses/gpl-license.html 9 + * http://www.gnu.org/copyleft/gpl.html 10 + */ 11 + 12 + /dts-v1/; 13 + #include "imx27.dtsi" 14 + 15 + / { 16 + model = "Eukrea CPUIMX27"; 17 + compatible = "eukrea,cpuimx27", "fsl,imx27"; 18 + 19 + memory { 20 + reg = <0xa0000000 0x04000000>; 21 + }; 22 + 23 + clocks { 24 + #address-cells = <1>; 25 + #size-cells = <0>; 26 + compatible = "simple-bus"; 27 + 28 + clk14745600: clock@0 { 29 + #clock-cells = <0>; 30 + compatible = "fixed-clock"; 31 + clock-frequency = <14745600>; 32 + reg = <0>; 33 + }; 34 + }; 35 + }; 36 + 37 + &fec { 38 + pinctrl-names = "default"; 39 + pinctrl-0 = <&pinctrl_fec>; 40 + status = "okay"; 41 + }; 42 + 43 + &i2c1 { 44 + pinctrl-names = "default"; 45 + pinctrl-0 = <&pinctrl_i2c1>; 46 + status = "okay"; 47 + 48 + pcf8563@51 { 49 + compatible = "nxp,pcf8563"; 50 + reg = <0x51>; 51 + }; 52 + }; 53 + 54 + &nfc { 55 + pinctrl-names = "default"; 56 + pinctrl-0 = <&pinctrl_nfc>; 57 + nand-bus-width = <8>; 58 + nand-ecc-mode = "hw"; 59 + nand-on-flash-bbt; 60 + status = "okay"; 61 + }; 62 + 63 + &owire { 64 + pinctrl-names = "default"; 65 + pinctrl-0 = <&pinctrl_owire>; 66 + status = "okay"; 67 + }; 68 + 69 + &sdhci2 { 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&pinctrl_sdhc2>; 72 + bus-width = <4>; 73 + non-removable; 74 + status = "okay"; 75 + }; 76 + 77 + &uart4 { 78 + pinctrl-names = "default"; 79 + pinctrl-0 = <&pinctrl_uart4>; 80 + fsl,uart-has-rtscts; 81 + status = "okay"; 82 + }; 83 + 84 + &usbh2 { 85 + pinctrl-names = "default"; 86 + pinctrl-0 = <&pinctrl_usbh2>; 87 + dr_mode = "host"; 88 + phy_type = "ulpi"; 89 + disable-over-current; 90 + status = "okay"; 91 + }; 92 + 93 + &usbotg { 94 + pinctrl-names = "default"; 95 + pinctrl-0 = <&pinctrl_usbotg>; 96 + dr_mode = "otg"; 97 + phy_type = "ulpi"; 98 + disable-over-current; 99 + status = "okay"; 100 + }; 101 + 102 + &weim { 103 + status = "okay"; 104 + 105 + nor: nor@0,0 { 106 + #address-cells = <1>; 107 + #size-cells = <1>; 108 + compatible = "cfi-flash"; 109 + reg = <0 0x00000000 0x04000000>; 110 + bank-width = <2>; 111 + linux,mtd-name = "physmap-flash.0"; 112 + fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; 113 + }; 114 + 115 + uart8250@3,200000 { 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&pinctrl_uart8250_1>; 118 + compatible = "ns8250"; 119 + clocks = <&clk14745600>; 120 + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 121 + interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; 122 + reg = <3 0x200000 0x1000>; 123 + reg-shift = <1>; 124 + reg-io-width = <1>; 125 + no-loopback-test; 126 + }; 127 + 128 + uart8250@3,400000 { 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_uart8250_2>; 131 + compatible = "ns8250"; 132 + clocks = <&clk14745600>; 133 + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 134 + interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; 135 + reg = <3 0x400000 0x1000>; 136 + reg-shift = <1>; 137 + reg-io-width = <1>; 138 + no-loopback-test; 139 + }; 140 + 141 + uart8250@3,800000 { 142 + pinctrl-names = "default"; 143 + pinctrl-0 = <&pinctrl_uart8250_3>; 144 + compatible = "ns8250"; 145 + clocks = <&clk14745600>; 146 + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 147 + interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; 148 + reg = <3 0x800000 0x1000>; 149 + reg-shift = <1>; 150 + reg-io-width = <1>; 151 + no-loopback-test; 152 + }; 153 + 154 + uart8250@3,1000000 { 155 + pinctrl-names = "default"; 156 + pinctrl-0 = <&pinctrl_uart8250_4>; 157 + compatible = "ns8250"; 158 + clocks = <&clk14745600>; 159 + fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 160 + interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; 161 + reg = <3 0x1000000 0x1000>; 162 + reg-shift = <1>; 163 + reg-io-width = <1>; 164 + no-loopback-test; 165 + }; 166 + }; 167 + 168 + &iomuxc { 169 + imx27-eukrea-cpuimx27 { 170 + pinctrl_fec: fecgrp { 171 + fsl,pins = < 172 + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 173 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 174 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 175 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 176 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 177 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 178 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 179 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 180 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 181 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 182 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 183 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 184 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 185 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 186 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 187 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 188 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 189 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 190 + >; 191 + }; 192 + 193 + pinctrl_i2c1: i2c1grp { 194 + fsl,pins = < 195 + MX27_PAD_I2C_DATA__I2C_DATA 0x0 196 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 197 + >; 198 + }; 199 + 200 + pinctrl_nfc: nfcgrp { 201 + fsl,pins = < 202 + MX27_PAD_NFRB__NFRB 0x0 203 + MX27_PAD_NFCLE__NFCLE 0x0 204 + MX27_PAD_NFWP_B__NFWP_B 0x0 205 + MX27_PAD_NFCE_B__NFCE_B 0x0 206 + MX27_PAD_NFALE__NFALE 0x0 207 + MX27_PAD_NFRE_B__NFRE_B 0x0 208 + MX27_PAD_NFWE_B__NFWE_B 0x0 209 + >; 210 + }; 211 + 212 + pinctrl_owire: owiregrp { 213 + fsl,pins = < 214 + MX27_PAD_RTCK__OWIRE 0x0 215 + >; 216 + }; 217 + 218 + pinctrl_sdhc2: sdhc2grp { 219 + fsl,pins = < 220 + MX27_PAD_SD2_CLK__SD2_CLK 0x0 221 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 222 + MX27_PAD_SD2_D0__SD2_D0 0x0 223 + MX27_PAD_SD2_D1__SD2_D1 0x0 224 + MX27_PAD_SD2_D2__SD2_D2 0x0 225 + MX27_PAD_SD2_D3__SD2_D3 0x0 226 + >; 227 + }; 228 + 229 + pinctrl_uart4: uart4grp { 230 + fsl,pins = < 231 + MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 232 + MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 233 + MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 234 + MX27_PAD_USBH1_FS__UART4_RTS 0x0 235 + >; 236 + }; 237 + 238 + pinctrl_uart8250_1: uart82501grp { 239 + fsl,pins = < 240 + MX27_PAD_USB_PWR__GPIO2_23 0x0 241 + >; 242 + }; 243 + 244 + pinctrl_uart8250_2: uart82502grp { 245 + fsl,pins = < 246 + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 247 + >; 248 + }; 249 + 250 + pinctrl_uart8250_3: uart82503grp { 251 + fsl,pins = < 252 + MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 253 + >; 254 + }; 255 + 256 + pinctrl_uart8250_4: uart82504grp { 257 + fsl,pins = < 258 + MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 259 + >; 260 + }; 261 + 262 + pinctrl_usbh2: usbh2grp { 263 + fsl,pins = < 264 + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 265 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 266 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 267 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 268 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 269 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 270 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 271 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 272 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 273 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 274 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 275 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 276 + >; 277 + }; 278 + 279 + pinctrl_usbotg: usbotggrp { 280 + fsl,pins = < 281 + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 282 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 283 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 284 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 285 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 286 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 287 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 288 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 289 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 290 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 291 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 292 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 293 + >; 294 + }; 295 + }; 296 + };
+274
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
··· 1 + /* 2 + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3 + * 4 + * The code contained herein is licensed under the GNU General Public 5 + * License. You may obtain a copy of the GNU General Public License 6 + * Version 2 or later at the following locations: 7 + * 8 + * http://www.opensource.org/licenses/gpl-license.html 9 + * http://www.gnu.org/copyleft/gpl.html 10 + */ 11 + 12 + #include "imx27-eukrea-cpuimx27.dtsi" 13 + 14 + / { 15 + model = "Eukrea MBIMXSD27"; 16 + compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; 17 + 18 + display0: CMO-QVGA { 19 + model = "CMO-QVGA"; 20 + native-mode = <&timing0>; 21 + bits-per-pixel = <16>; 22 + fsl,pcr = <0xfad08b80>; 23 + 24 + display-timings { 25 + timing0: 320x240 { 26 + clock-frequency = <6500000>; 27 + hactive = <320>; 28 + vactive = <240>; 29 + hback-porch = <20>; 30 + hsync-len = <30>; 31 + hfront-porch = <38>; 32 + vback-porch = <4>; 33 + vsync-len = <3>; 34 + vfront-porch = <15>; 35 + }; 36 + }; 37 + }; 38 + 39 + backlight { 40 + compatible = "gpio-backlight"; 41 + pinctrl-names = "default"; 42 + pinctrl-0 = <&pinctrl_backlight>; 43 + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 44 + }; 45 + 46 + leds { 47 + compatible = "gpio-leds"; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&pinctrl_gpioleds>; 50 + 51 + led1 { 52 + label = "system::live"; 53 + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; 54 + linux,default-trigger = "heartbeat"; 55 + }; 56 + 57 + led2 { 58 + label = "system::user"; 59 + gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; 60 + }; 61 + }; 62 + 63 + regulators { 64 + #address-cells = <1>; 65 + #size-cells = <0>; 66 + compatible = "simple-bus"; 67 + 68 + reg_lcd: regulator@0 { 69 + pinctrl-names = "default"; 70 + pinctrl-0 = <&pinctrl_lcdreg>; 71 + compatible = "regulator-fixed"; 72 + reg = <0>; 73 + regulator-name = "LCD"; 74 + regulator-min-microvolt = <5000000>; 75 + regulator-max-microvolt = <5000000>; 76 + gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; 77 + enable-active-high; 78 + }; 79 + }; 80 + }; 81 + 82 + &cspi1 { 83 + pinctrl-0 = <&pinctrl_cspi1>; 84 + fsl,spi-num-chipselects = <1>; 85 + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 86 + status = "okay"; 87 + 88 + ads7846 { 89 + compatible = "ti,ads7846"; 90 + pinctrl-names = "default"; 91 + pinctrl-0 = <&pinctrl_touch>; 92 + reg = <0>; 93 + interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; 94 + spi-cpol; 95 + spi-max-frequency = <1500000>; 96 + ti,keep-vref-on; 97 + }; 98 + }; 99 + 100 + &fb { 101 + pinctrl-names = "default"; 102 + pinctrl-0 = <&pinctrl_imxfb>; 103 + display = <&display0>; 104 + lcd-supply = <&reg_lcd>; 105 + fsl,dmacr = <0x00040060>; 106 + fsl,lscr1 = <0x00120300>; 107 + fsl,lpccr = <0x00a903ff>; 108 + status = "okay"; 109 + }; 110 + 111 + &i2c1 { 112 + codec: codec@1a { 113 + compatible = "ti,tlv320aic23"; 114 + reg = <0x1a>; 115 + }; 116 + }; 117 + 118 + &kpp { 119 + linux,keymap = < 120 + MATRIX_KEY(0, 0, KEY_UP) 121 + MATRIX_KEY(0, 1, KEY_DOWN) 122 + MATRIX_KEY(1, 0, KEY_RIGHT) 123 + MATRIX_KEY(1, 1, KEY_LEFT) 124 + >; 125 + status = "okay"; 126 + }; 127 + 128 + &sdhci1 { 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_sdhc1>; 131 + bus-width = <4>; 132 + status = "okay"; 133 + }; 134 + 135 + &ssi1 { 136 + pinctrl-names = "default"; 137 + pinctrl-0 = <&pinctrl_ssi1>; 138 + fsl,mode = "i2s-slave"; 139 + codec-handle = <&codec>; 140 + status = "okay"; 141 + }; 142 + 143 + &uart1 { 144 + fsl,uart-has-rtscts; 145 + pinctrl-names = "default"; 146 + pinctrl-0 = <&pinctrl_uart1>; 147 + status = "okay"; 148 + }; 149 + 150 + &uart2 { 151 + fsl,uart-has-rtscts; 152 + pinctrl-names = "default"; 153 + pinctrl-0 = <&pinctrl_uart2>; 154 + status = "okay"; 155 + }; 156 + 157 + &uart3 { 158 + fsl,uart-has-rtscts; 159 + pinctrl-names = "default"; 160 + pinctrl-0 = <&pinctrl_uart3>; 161 + status = "okay"; 162 + }; 163 + 164 + &iomuxc { 165 + imx27-eukrea-cpuimx27-baseboard { 166 + pinctrl_cspi1: cspi1grp { 167 + fsl,pins = < 168 + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 169 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 170 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 171 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ 172 + >; 173 + }; 174 + 175 + pinctrl_backlight: backlightgrp { 176 + fsl,pins = < 177 + MX27_PAD_PWMO__GPIO5_5 0x0 178 + >; 179 + }; 180 + 181 + pinctrl_gpioleds: gpioledsgrp { 182 + fsl,pins = < 183 + MX27_PAD_PC_PWRON__GPIO6_16 0x0 184 + MX27_PAD_PC_CD2_B__GPIO6_19 0x0 185 + >; 186 + }; 187 + 188 + pinctrl_imxfb: imxfbgrp { 189 + fsl,pins = < 190 + MX27_PAD_LD0__LD0 0x0 191 + MX27_PAD_LD1__LD1 0x0 192 + MX27_PAD_LD2__LD2 0x0 193 + MX27_PAD_LD3__LD3 0x0 194 + MX27_PAD_LD4__LD4 0x0 195 + MX27_PAD_LD5__LD5 0x0 196 + MX27_PAD_LD6__LD6 0x0 197 + MX27_PAD_LD7__LD7 0x0 198 + MX27_PAD_LD8__LD8 0x0 199 + MX27_PAD_LD9__LD9 0x0 200 + MX27_PAD_LD10__LD10 0x0 201 + MX27_PAD_LD11__LD11 0x0 202 + MX27_PAD_LD12__LD12 0x0 203 + MX27_PAD_LD13__LD13 0x0 204 + MX27_PAD_LD14__LD14 0x0 205 + MX27_PAD_LD15__LD15 0x0 206 + MX27_PAD_LD16__LD16 0x0 207 + MX27_PAD_LD17__LD17 0x0 208 + MX27_PAD_CONTRAST__CONTRAST 0x0 209 + MX27_PAD_OE_ACD__OE_ACD 0x0 210 + MX27_PAD_HSYNC__HSYNC 0x0 211 + MX27_PAD_VSYNC__VSYNC 0x0 212 + >; 213 + }; 214 + 215 + pinctrl_lcdreg: lcdreggrp { 216 + fsl,pins = < 217 + MX27_PAD_CLS__GPIO1_25 0x0 218 + >; 219 + }; 220 + 221 + pinctrl_sdhc1: sdhc1grp { 222 + fsl,pins = < 223 + MX27_PAD_SD1_CLK__SD1_CLK 0x0 224 + MX27_PAD_SD1_CMD__SD1_CMD 0x0 225 + MX27_PAD_SD1_D0__SD1_D0 0x0 226 + MX27_PAD_SD1_D1__SD1_D1 0x0 227 + MX27_PAD_SD1_D2__SD1_D2 0x0 228 + MX27_PAD_SD1_D3__SD1_D3 0x0 229 + >; 230 + }; 231 + 232 + pinctrl_ssi1: ssi1grp { 233 + fsl,pins = < 234 + MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 235 + MX27_PAD_SSI4_FS__SSI4_FS 0x0 236 + MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 237 + MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 238 + >; 239 + }; 240 + 241 + pinctrl_touch: touchgrp { 242 + fsl,pins = < 243 + MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ 244 + >; 245 + }; 246 + 247 + pinctrl_uart1: uart1grp { 248 + fsl,pins = < 249 + MX27_PAD_UART1_TXD__UART1_TXD 0x0 250 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 251 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 252 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 253 + >; 254 + }; 255 + 256 + pinctrl_uart2: uart2grp { 257 + fsl,pins = < 258 + MX27_PAD_UART2_TXD__UART2_TXD 0x0 259 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 260 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 261 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 262 + >; 263 + }; 264 + 265 + pinctrl_uart3: uart3grp { 266 + fsl,pins = < 267 + MX27_PAD_UART3_TXD__UART3_TXD 0x0 268 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 269 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 270 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 271 + >; 272 + }; 273 + }; 274 + };