tjh.dev / kernel
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drm/amdgpu: add mmhub v3_0_1 headers

Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Huang Rui and committed by
Alex Deucher d5771670 16600b7d

+9252
+1769
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _mmhub_3_0_1_OFFSET_HEADER 24 + #define _mmhub_3_0_1_OFFSET_HEADER 25 + 26 + 27 + 28 + // addressBlock: mmhub_dagbdec 29 + // base address: 0x68000 30 + #define regDAGB0_RDCLI0 0x0000 31 + #define regDAGB0_RDCLI0_BASE_IDX 1 32 + #define regDAGB0_RDCLI1 0x0001 33 + #define regDAGB0_RDCLI1_BASE_IDX 1 34 + #define regDAGB0_RDCLI2 0x0002 35 + #define regDAGB0_RDCLI2_BASE_IDX 1 36 + #define regDAGB0_RDCLI3 0x0003 37 + #define regDAGB0_RDCLI3_BASE_IDX 1 38 + #define regDAGB0_RDCLI4 0x0004 39 + #define regDAGB0_RDCLI4_BASE_IDX 1 40 + #define regDAGB0_RDCLI5 0x0005 41 + #define regDAGB0_RDCLI5_BASE_IDX 1 42 + #define regDAGB0_RDCLI6 0x0006 43 + #define regDAGB0_RDCLI6_BASE_IDX 1 44 + #define regDAGB0_RDCLI7 0x0007 45 + #define regDAGB0_RDCLI7_BASE_IDX 1 46 + #define regDAGB0_RDCLI8 0x0008 47 + #define regDAGB0_RDCLI8_BASE_IDX 1 48 + #define regDAGB0_RDCLI9 0x0009 49 + #define regDAGB0_RDCLI9_BASE_IDX 1 50 + #define regDAGB0_RDCLI10 0x000a 51 + #define regDAGB0_RDCLI10_BASE_IDX 1 52 + #define regDAGB0_RDCLI11 0x000b 53 + #define regDAGB0_RDCLI11_BASE_IDX 1 54 + #define regDAGB0_RDCLI12 0x000c 55 + #define regDAGB0_RDCLI12_BASE_IDX 1 56 + #define regDAGB0_RDCLI13 0x000d 57 + #define regDAGB0_RDCLI13_BASE_IDX 1 58 + #define regDAGB0_RDCLI14 0x000e 59 + #define regDAGB0_RDCLI14_BASE_IDX 1 60 + #define regDAGB0_RDCLI15 0x000f 61 + #define regDAGB0_RDCLI15_BASE_IDX 1 62 + #define regDAGB0_RDCLI16 0x0010 63 + #define regDAGB0_RDCLI16_BASE_IDX 1 64 + #define regDAGB0_RDCLI17 0x0011 65 + #define regDAGB0_RDCLI17_BASE_IDX 1 66 + #define regDAGB0_RDCLI18 0x0012 67 + #define regDAGB0_RDCLI18_BASE_IDX 1 68 + #define regDAGB0_RDCLI19 0x0013 69 + #define regDAGB0_RDCLI19_BASE_IDX 1 70 + #define regDAGB0_RDCLI20 0x0014 71 + #define regDAGB0_RDCLI20_BASE_IDX 1 72 + #define regDAGB0_RDCLI21 0x0015 73 + #define regDAGB0_RDCLI21_BASE_IDX 1 74 + #define regDAGB0_RDCLI22 0x0016 75 + #define regDAGB0_RDCLI22_BASE_IDX 1 76 + #define regDAGB0_RDCLI23 0x0017 77 + #define regDAGB0_RDCLI23_BASE_IDX 1 78 + #define regDAGB0_RDCLI24 0x0018 79 + #define regDAGB0_RDCLI24_BASE_IDX 1 80 + #define regDAGB0_RDCLI25 0x0019 81 + #define regDAGB0_RDCLI25_BASE_IDX 1 82 + #define regDAGB0_RDCLI26 0x001a 83 + #define regDAGB0_RDCLI26_BASE_IDX 1 84 + #define regDAGB0_RDCLI27 0x001b 85 + #define regDAGB0_RDCLI27_BASE_IDX 1 86 + #define regDAGB0_RDCLI28 0x001c 87 + #define regDAGB0_RDCLI28_BASE_IDX 1 88 + #define regDAGB0_RDCLI29 0x001d 89 + #define regDAGB0_RDCLI29_BASE_IDX 1 90 + #define regDAGB0_RD_CNTL 0x001e 91 + #define regDAGB0_RD_CNTL_BASE_IDX 1 92 + #define regDAGB0_RD_IO_CNTL 0x001f 93 + #define regDAGB0_RD_IO_CNTL_BASE_IDX 1 94 + #define regDAGB0_RD_GMI_CNTL 0x0020 95 + #define regDAGB0_RD_GMI_CNTL_BASE_IDX 1 96 + #define regDAGB0_RD_ADDR_DAGB 0x0021 97 + #define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1 98 + #define regDAGB0_RD_CGTT_CLK_CTRL 0x0022 99 + #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 100 + #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0023 101 + #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 102 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0024 103 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 104 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0025 105 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 106 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0026 107 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 108 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0027 109 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 110 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0028 111 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 112 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0029 113 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 114 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002a 115 + #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 116 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002b 117 + #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 118 + #define regDAGB0_RD_VC0_CNTL 0x002c 119 + #define regDAGB0_RD_VC0_CNTL_BASE_IDX 1 120 + #define regDAGB0_RD_VC1_CNTL 0x002d 121 + #define regDAGB0_RD_VC1_CNTL_BASE_IDX 1 122 + #define regDAGB0_RD_VC2_CNTL 0x002e 123 + #define regDAGB0_RD_VC2_CNTL_BASE_IDX 1 124 + #define regDAGB0_RD_VC3_CNTL 0x002f 125 + #define regDAGB0_RD_VC3_CNTL_BASE_IDX 1 126 + #define regDAGB0_RD_VC4_CNTL 0x0030 127 + #define regDAGB0_RD_VC4_CNTL_BASE_IDX 1 128 + #define regDAGB0_RD_VC5_CNTL 0x0031 129 + #define regDAGB0_RD_VC5_CNTL_BASE_IDX 1 130 + #define regDAGB0_RD_IO_VC_CNTL 0x0032 131 + #define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 1 132 + #define regDAGB0_RD_GMI_VC_CNTL 0x0033 133 + #define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 1 134 + #define regDAGB0_RD_CNTL_MISC 0x0034 135 + #define regDAGB0_RD_CNTL_MISC_BASE_IDX 1 136 + #define regDAGB0_RD_TLB_CREDIT 0x0035 137 + #define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1 138 + #define regDAGB0_RDCLI_ASK_PENDING 0x0036 139 + #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 140 + #define regDAGB0_RDCLI_GO_PENDING 0x0037 141 + #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 142 + #define regDAGB0_RDCLI_GBLSEND_PENDING 0x0038 143 + #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 144 + #define regDAGB0_RDCLI_TLB_PENDING 0x0039 145 + #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 146 + #define regDAGB0_RDCLI_OARB_PENDING 0x003a 147 + #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 148 + #define regDAGB0_RDCLI_ASK2ARB_PENDING 0x003b 149 + #define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 1 150 + #define regDAGB0_RDCLI_ASK2DF_PENDING 0x003c 151 + #define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1 152 + #define regDAGB0_RDCLI_OSD_PENDING 0x003d 153 + #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 154 + #define regDAGB0_RDCLI_ASK_OSD_PENDING 0x003e 155 + #define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 156 + #define regDAGB0_WRCLI0 0x003f 157 + #define regDAGB0_WRCLI0_BASE_IDX 1 158 + #define regDAGB0_WRCLI1 0x0040 159 + #define regDAGB0_WRCLI1_BASE_IDX 1 160 + #define regDAGB0_WRCLI2 0x0041 161 + #define regDAGB0_WRCLI2_BASE_IDX 1 162 + #define regDAGB0_WRCLI3 0x0042 163 + #define regDAGB0_WRCLI3_BASE_IDX 1 164 + #define regDAGB0_WRCLI4 0x0043 165 + #define regDAGB0_WRCLI4_BASE_IDX 1 166 + #define regDAGB0_WRCLI5 0x0044 167 + #define regDAGB0_WRCLI5_BASE_IDX 1 168 + #define regDAGB0_WRCLI6 0x0045 169 + #define regDAGB0_WRCLI6_BASE_IDX 1 170 + #define regDAGB0_WRCLI7 0x0046 171 + #define regDAGB0_WRCLI7_BASE_IDX 1 172 + #define regDAGB0_WRCLI8 0x0047 173 + #define regDAGB0_WRCLI8_BASE_IDX 1 174 + #define regDAGB0_WRCLI9 0x0048 175 + #define regDAGB0_WRCLI9_BASE_IDX 1 176 + #define regDAGB0_WRCLI10 0x0049 177 + #define regDAGB0_WRCLI10_BASE_IDX 1 178 + #define regDAGB0_WRCLI11 0x004a 179 + #define regDAGB0_WRCLI11_BASE_IDX 1 180 + #define regDAGB0_WRCLI12 0x004b 181 + #define regDAGB0_WRCLI12_BASE_IDX 1 182 + #define regDAGB0_WRCLI13 0x004c 183 + #define regDAGB0_WRCLI13_BASE_IDX 1 184 + #define regDAGB0_WRCLI14 0x004d 185 + #define regDAGB0_WRCLI14_BASE_IDX 1 186 + #define regDAGB0_WRCLI15 0x004e 187 + #define regDAGB0_WRCLI15_BASE_IDX 1 188 + #define regDAGB0_WRCLI16 0x004f 189 + #define regDAGB0_WRCLI16_BASE_IDX 1 190 + #define regDAGB0_WRCLI17 0x0050 191 + #define regDAGB0_WRCLI17_BASE_IDX 1 192 + #define regDAGB0_WRCLI18 0x0051 193 + #define regDAGB0_WRCLI18_BASE_IDX 1 194 + #define regDAGB0_WRCLI19 0x0052 195 + #define regDAGB0_WRCLI19_BASE_IDX 1 196 + #define regDAGB0_WRCLI20 0x0053 197 + #define regDAGB0_WRCLI20_BASE_IDX 1 198 + #define regDAGB0_WRCLI21 0x0054 199 + #define regDAGB0_WRCLI21_BASE_IDX 1 200 + #define regDAGB0_WRCLI22 0x0055 201 + #define regDAGB0_WRCLI22_BASE_IDX 1 202 + #define regDAGB0_WRCLI23 0x0056 203 + #define regDAGB0_WRCLI23_BASE_IDX 1 204 + #define regDAGB0_WRCLI24 0x0057 205 + #define regDAGB0_WRCLI24_BASE_IDX 1 206 + #define regDAGB0_WRCLI25 0x0058 207 + #define regDAGB0_WRCLI25_BASE_IDX 1 208 + #define regDAGB0_WRCLI26 0x0059 209 + #define regDAGB0_WRCLI26_BASE_IDX 1 210 + #define regDAGB0_WRCLI27 0x005a 211 + #define regDAGB0_WRCLI27_BASE_IDX 1 212 + #define regDAGB0_WRCLI28 0x005b 213 + #define regDAGB0_WRCLI28_BASE_IDX 1 214 + #define regDAGB0_WRCLI29 0x005c 215 + #define regDAGB0_WRCLI29_BASE_IDX 1 216 + #define regDAGB0_WR_CNTL 0x005d 217 + #define regDAGB0_WR_CNTL_BASE_IDX 1 218 + #define regDAGB0_WR_IO_CNTL 0x005e 219 + #define regDAGB0_WR_IO_CNTL_BASE_IDX 1 220 + #define regDAGB0_WR_GMI_CNTL 0x005f 221 + #define regDAGB0_WR_GMI_CNTL_BASE_IDX 1 222 + #define regDAGB0_WR_ADDR_DAGB 0x0060 223 + #define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1 224 + #define regDAGB0_WR_CGTT_CLK_CTRL 0x0061 225 + #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 226 + #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0062 227 + #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 228 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0063 229 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 230 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0064 231 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 232 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0065 233 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 234 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0066 235 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 236 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0067 237 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 238 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0068 239 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 240 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x0069 241 + #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 242 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006a 243 + #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 244 + #define regDAGB0_WR_DATA_DAGB 0x006b 245 + #define regDAGB0_WR_DATA_DAGB_BASE_IDX 1 246 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x006c 247 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 248 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x006d 249 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 250 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x006e 251 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 252 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x006f 253 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 254 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0070 255 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 256 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0071 257 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 258 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0072 259 + #define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 260 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0073 261 + #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 262 + #define regDAGB0_WR_VC0_CNTL 0x0074 263 + #define regDAGB0_WR_VC0_CNTL_BASE_IDX 1 264 + #define regDAGB0_WR_VC1_CNTL 0x0075 265 + #define regDAGB0_WR_VC1_CNTL_BASE_IDX 1 266 + #define regDAGB0_WR_VC2_CNTL 0x0076 267 + #define regDAGB0_WR_VC2_CNTL_BASE_IDX 1 268 + #define regDAGB0_WR_VC3_CNTL 0x0077 269 + #define regDAGB0_WR_VC3_CNTL_BASE_IDX 1 270 + #define regDAGB0_WR_VC4_CNTL 0x0078 271 + #define regDAGB0_WR_VC4_CNTL_BASE_IDX 1 272 + #define regDAGB0_WR_VC5_CNTL 0x0079 273 + #define regDAGB0_WR_VC5_CNTL_BASE_IDX 1 274 + #define regDAGB0_WR_IO_VC_CNTL 0x007a 275 + #define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 1 276 + #define regDAGB0_WR_GMI_VC_CNTL 0x007b 277 + #define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 1 278 + #define regDAGB0_WR_CNTL_MISC 0x007c 279 + #define regDAGB0_WR_CNTL_MISC_BASE_IDX 1 280 + #define regDAGB0_WR_TLB_CREDIT 0x007d 281 + #define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1 282 + #define regDAGB0_WR_DATA_CREDIT 0x007e 283 + #define regDAGB0_WR_DATA_CREDIT_BASE_IDX 1 284 + #define regDAGB0_WR_MISC_CREDIT 0x007f 285 + #define regDAGB0_WR_MISC_CREDIT_BASE_IDX 1 286 + #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0080 287 + #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 288 + #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0081 289 + #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 290 + #define regDAGB0_WRCLI_ASK_PENDING 0x0082 291 + #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 292 + #define regDAGB0_WRCLI_GO_PENDING 0x0083 293 + #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 294 + #define regDAGB0_WRCLI_GBLSEND_PENDING 0x0084 295 + #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 296 + #define regDAGB0_WRCLI_TLB_PENDING 0x0085 297 + #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 298 + #define regDAGB0_WRCLI_OARB_PENDING 0x0086 299 + #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 300 + #define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0087 301 + #define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 1 302 + #define regDAGB0_WRCLI_ASK2DF_PENDING 0x0088 303 + #define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1 304 + #define regDAGB0_WRCLI_OSD_PENDING 0x0089 305 + #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 306 + #define regDAGB0_WRCLI_ASK_OSD_PENDING 0x008a 307 + #define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1 308 + #define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x008b 309 + #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 310 + #define regDAGB0_WRCLI_DBUS_GO_PENDING 0x008c 311 + #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 312 + #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x008d 313 + #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 314 + #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x008e 315 + #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 316 + #define regDAGB0_DAGB_DLY 0x008f 317 + #define regDAGB0_DAGB_DLY_BASE_IDX 1 318 + #define regDAGB0_CNTL_MISC 0x0090 319 + #define regDAGB0_CNTL_MISC_BASE_IDX 1 320 + #define regDAGB0_CNTL_MISC2 0x0091 321 + #define regDAGB0_CNTL_MISC2_BASE_IDX 1 322 + #define regDAGB0_FIFO_EMPTY 0x0092 323 + #define regDAGB0_FIFO_EMPTY_BASE_IDX 1 324 + #define regDAGB0_FIFO_FULL 0x0093 325 + #define regDAGB0_FIFO_FULL_BASE_IDX 1 326 + #define regDAGB0_RD_CREDITS_FULL 0x0094 327 + #define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1 328 + #define regDAGB0_WR_CREDITS_FULL 0x0095 329 + #define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1 330 + #define regDAGB0_PERFCOUNTER_LO 0x0096 331 + #define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1 332 + #define regDAGB0_PERFCOUNTER_HI 0x0097 333 + #define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1 334 + #define regDAGB0_PERFCOUNTER0_CFG 0x0098 335 + #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 336 + #define regDAGB0_PERFCOUNTER1_CFG 0x0099 337 + #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 338 + #define regDAGB0_PERFCOUNTER2_CFG 0x009a 339 + #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 340 + #define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x009b 341 + #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 342 + #define regDAGB0_L1TLB_REG_RW 0x009c 343 + #define regDAGB0_L1TLB_REG_RW_BASE_IDX 1 344 + #define regDAGB0_RESERVE1 0x009d 345 + #define regDAGB0_RESERVE1_BASE_IDX 1 346 + #define regDAGB0_RESERVE2 0x009e 347 + #define regDAGB0_RESERVE2_BASE_IDX 1 348 + #define regDAGB0_RESERVE3 0x009f 349 + #define regDAGB0_RESERVE3_BASE_IDX 1 350 + #define regDAGB0_RESERVE4 0x00a0 351 + #define regDAGB0_RESERVE4_BASE_IDX 1 352 + #define regDAGB0_SDP_RD_BW_CNTL 0x00a1 353 + #define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1 354 + #define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00a2 355 + #define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 356 + #define regDAGB0_SDP_RD_PRIORITY 0x00a3 357 + #define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1 358 + #define regDAGB0_SDP_WR_PRIORITY 0x00a4 359 + #define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1 360 + #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00a5 361 + #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 362 + #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00a6 363 + #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1 364 + #define regDAGB0_SDP_ENABLE 0x00a7 365 + #define regDAGB0_SDP_ENABLE_BASE_IDX 1 366 + #define regDAGB0_SDP_CREDITS 0x00a8 367 + #define regDAGB0_SDP_CREDITS_BASE_IDX 1 368 + #define regDAGB0_SDP_TAG_RESERVE0 0x00a9 369 + #define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1 370 + #define regDAGB0_SDP_TAG_RESERVE1 0x00aa 371 + #define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1 372 + #define regDAGB0_SDP_VCC_RESERVE0 0x00ab 373 + #define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1 374 + #define regDAGB0_SDP_VCC_RESERVE1 0x00ac 375 + #define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1 376 + #define regDAGB0_SDP_ERR_STATUS 0x00ad 377 + #define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1 378 + #define regDAGB0_SDP_REQ_CNTL 0x00ae 379 + #define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1 380 + #define regDAGB0_SDP_MISC_AON 0x00af 381 + #define regDAGB0_SDP_MISC_AON_BASE_IDX 1 382 + #define regDAGB0_SDP_MISC 0x00b0 383 + #define regDAGB0_SDP_MISC_BASE_IDX 1 384 + #define regDAGB0_SDP_MISC2 0x00b1 385 + #define regDAGB0_SDP_MISC2_BASE_IDX 1 386 + #define regDAGB0_SDP_VCD_RESERVE0 0x00b3 387 + #define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1 388 + #define regDAGB0_SDP_VCD_RESERVE1 0x00b4 389 + #define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1 390 + #define regDAGB0_SDP_ARB_CNTL0 0x00b5 391 + #define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1 392 + #define regDAGB0_SDP_ARB_CNTL1 0x00b6 393 + #define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1 394 + #define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b7 395 + #define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1 396 + #define regDAGB0_SDP_LATENCY_SAMPLING 0x00b8 397 + #define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1 398 + 399 + 400 + // addressBlock: mmhub_pctldec 401 + // base address: 0x68e00 402 + #define regPCTL_CTRL 0x0380 403 + #define regPCTL_CTRL_BASE_IDX 1 404 + #define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 405 + #define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 406 + #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 407 + #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 408 + #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 409 + #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 410 + #define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 411 + #define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 412 + #define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 413 + #define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 414 + #define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 415 + #define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 416 + #define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 417 + #define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 418 + #define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 419 + #define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 420 + #define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 421 + #define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 422 + #define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a 423 + #define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 424 + #define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b 425 + #define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 426 + #define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c 427 + #define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 428 + #define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d 429 + #define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 430 + #define regPCTL_UTCL2_MISC 0x038e 431 + #define regPCTL_UTCL2_MISC_BASE_IDX 1 432 + #define regPCTL_SLICE0_MISC 0x038f 433 + #define regPCTL_SLICE0_MISC_BASE_IDX 1 434 + #define regPCTL_SLICE1_MISC 0x0390 435 + #define regPCTL_SLICE1_MISC_BASE_IDX 1 436 + #define regPCTL_RENG_CTRL 0x0391 437 + #define regPCTL_RENG_CTRL_BASE_IDX 1 438 + #define regPCTL_UTCL2_RENG_EXECUTE 0x0392 439 + #define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 440 + #define regPCTL_SLICE0_RENG_EXECUTE 0x0393 441 + #define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 442 + #define regPCTL_SLICE1_RENG_EXECUTE 0x0394 443 + #define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 444 + #define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 445 + #define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 446 + #define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 447 + #define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 448 + #define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 449 + #define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 450 + #define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 451 + #define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 452 + #define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 453 + #define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 454 + #define regPCTL_SLICE1_RENG_RAM_DATA 0x039a 455 + #define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 456 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 457 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 458 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 459 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 460 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 461 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 462 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e 463 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 464 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f 465 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 466 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 467 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 468 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 469 + #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 470 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 471 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 472 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 473 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 474 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 475 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 476 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 477 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 478 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 479 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 480 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 481 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 482 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 483 + #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 484 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 485 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 486 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa 487 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 488 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab 489 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 490 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac 491 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 492 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad 493 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 494 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae 495 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 496 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af 497 + #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 498 + #define regPCTL_STATUS 0x03b0 499 + #define regPCTL_STATUS_BASE_IDX 1 500 + #define regPCTL_PERFCOUNTER_LO 0x03b1 501 + #define regPCTL_PERFCOUNTER_LO_BASE_IDX 1 502 + #define regPCTL_PERFCOUNTER_HI 0x03b2 503 + #define regPCTL_PERFCOUNTER_HI_BASE_IDX 1 504 + #define regPCTL_PERFCOUNTER0_CFG 0x03b3 505 + #define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 506 + #define regPCTL_PERFCOUNTER1_CFG 0x03b4 507 + #define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 508 + #define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 509 + #define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 510 + #define regPCTL_RESERVED_0 0x03b6 511 + #define regPCTL_RESERVED_0_BASE_IDX 1 512 + #define regPCTL_RESERVED_1 0x03b7 513 + #define regPCTL_RESERVED_1_BASE_IDX 1 514 + #define regPCTL_RESERVED_2 0x03b8 515 + #define regPCTL_RESERVED_2_BASE_IDX 1 516 + #define regPCTL_RESERVED_3 0x03b9 517 + #define regPCTL_RESERVED_3_BASE_IDX 1 518 + 519 + 520 + // addressBlock: mmhub_l1tlb_mmutcl1pfdec 521 + // base address: 0x69600 522 + #define regMMMC_VM_MX_L1_TLB0_STATUS 0x0588 523 + #define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 524 + #define regMMMC_VM_MX_L1_TLB1_STATUS 0x0589 525 + #define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 526 + #define regMMMC_VM_MX_L1_TLB2_STATUS 0x058a 527 + #define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 528 + #define regMMMC_VM_MX_L1_TLB3_STATUS 0x058b 529 + #define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 530 + #define regMMMC_VM_MX_L1_TLB4_STATUS 0x058c 531 + #define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 532 + #define regMMMC_VM_MX_L1_TLB5_STATUS 0x058d 533 + #define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 534 + #define regMMMC_VM_MX_L1_TLB6_STATUS 0x058e 535 + #define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 536 + #define regMMMC_VM_MX_L1_TLB7_STATUS 0x058f 537 + #define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 538 + 539 + 540 + // addressBlock: mmhub_l1tlb_mmutcl1pldec 541 + // base address: 0x69670 542 + #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c 543 + #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 544 + #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d 545 + #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 546 + #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e 547 + #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 548 + #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f 549 + #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 550 + #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 551 + #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 552 + 553 + 554 + // addressBlock: mmhub_l1tlb_mmutcl1prdec 555 + // base address: 0x69690 556 + #define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 557 + #define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 558 + #define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 559 + #define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 560 + 561 + 562 + // addressBlock: mmhub_l1tlb_mmvmtlspfdec 563 + // base address: 0x696c0 564 + #define regMMMC_VM_MX_L1_TLS0_CNTL 0x05b0 565 + #define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1 566 + #define regMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1 567 + #define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1 568 + #define regMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2 569 + #define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1 570 + #define regMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3 571 + #define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1 572 + #define regMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4 573 + #define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1 574 + #define regMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5 575 + #define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1 576 + #define regMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6 577 + #define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1 578 + #define regMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7 579 + #define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1 580 + #define regMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8 581 + #define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1 582 + #define regMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9 583 + #define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1 584 + #define regMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba 585 + #define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1 586 + #define regMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb 587 + #define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1 588 + #define regMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc 589 + #define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1 590 + #define regMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd 591 + #define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1 592 + #define regMMMC_VM_MX_L1_TLS0_CNTL13 0x05be 593 + #define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1 594 + #define regMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf 595 + #define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1 596 + #define regMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0 597 + #define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1 598 + #define regMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1 599 + #define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1 600 + #define regMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2 601 + #define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1 602 + #define regMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3 603 + #define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1 604 + #define regMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4 605 + #define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1 606 + #define regMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5 607 + #define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1 608 + #define regMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6 609 + #define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1 610 + #define regMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7 611 + #define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1 612 + #define regMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8 613 + #define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1 614 + #define regMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9 615 + #define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1 616 + #define regMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca 617 + #define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1 618 + #define regMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb 619 + #define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1 620 + #define regMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc 621 + #define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1 622 + #define regMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd 623 + #define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1 624 + #define regMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce 625 + #define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1 626 + #define regMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf 627 + #define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1 628 + #define regMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0 629 + #define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1 630 + #define regMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1 631 + #define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1 632 + #define regMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2 633 + #define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1 634 + #define regMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3 635 + #define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1 636 + #define regMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4 637 + #define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1 638 + #define regMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5 639 + #define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1 640 + #define regMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6 641 + #define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1 642 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7 643 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1 644 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8 645 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1 646 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9 647 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1 648 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da 649 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1 650 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db 651 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1 652 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc 653 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1 654 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd 655 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1 656 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de 657 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1 658 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df 659 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1 660 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0 661 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1 662 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1 663 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1 664 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2 665 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1 666 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3 667 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1 668 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4 669 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1 670 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5 671 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1 672 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6 673 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1 674 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7 675 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1 676 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8 677 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1 678 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9 679 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1 680 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea 681 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1 682 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb 683 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1 684 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec 685 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1 686 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed 687 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1 688 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee 689 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1 690 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef 691 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1 692 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0 693 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1 694 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1 695 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1 696 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2 697 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1 698 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3 699 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1 700 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4 701 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1 702 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5 703 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1 704 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6 705 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1 706 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7 707 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1 708 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8 709 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1 710 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9 711 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1 712 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa 713 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1 714 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb 715 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1 716 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc 717 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1 718 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd 719 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1 720 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe 721 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1 722 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff 723 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1 724 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600 725 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1 726 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601 727 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1 728 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602 729 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1 730 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603 731 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1 732 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604 733 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1 734 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605 735 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1 736 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606 737 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1 738 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607 739 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1 740 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608 741 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1 742 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609 743 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1 744 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a 745 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1 746 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b 747 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1 748 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c 749 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1 750 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d 751 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1 752 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e 753 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1 754 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f 755 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1 756 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610 757 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1 758 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611 759 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1 760 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612 761 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1 762 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613 763 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1 764 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614 765 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1 766 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615 767 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1 768 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616 769 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1 770 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617 771 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1 772 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618 773 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1 774 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619 775 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1 776 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a 777 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1 778 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b 779 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1 780 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c 781 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1 782 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d 783 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1 784 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e 785 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1 786 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f 787 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1 788 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620 789 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1 790 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621 791 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1 792 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622 793 + #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1 794 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623 795 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1 796 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624 797 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1 798 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625 799 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1 800 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626 801 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1 802 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627 803 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1 804 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628 805 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1 806 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629 807 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1 808 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a 809 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1 810 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b 811 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1 812 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c 813 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1 814 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d 815 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1 816 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e 817 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1 818 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f 819 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1 820 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630 821 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1 822 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631 823 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1 824 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632 825 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1 826 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633 827 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1 828 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634 829 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1 830 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635 831 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1 832 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636 833 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1 834 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637 835 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1 836 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638 837 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1 838 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639 839 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1 840 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a 841 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1 842 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b 843 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1 844 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c 845 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1 846 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d 847 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1 848 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e 849 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1 850 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f 851 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1 852 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640 853 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1 854 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641 855 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1 856 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642 857 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1 858 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643 859 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1 860 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644 861 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1 862 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645 863 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1 864 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646 865 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1 866 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647 867 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1 868 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648 869 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1 870 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649 871 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1 872 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a 873 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1 874 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b 875 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1 876 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c 877 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1 878 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d 879 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1 880 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e 881 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1 882 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f 883 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1 884 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650 885 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1 886 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651 887 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1 888 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652 889 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1 890 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653 891 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1 892 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654 893 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1 894 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655 895 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1 896 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656 897 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1 898 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657 899 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1 900 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658 901 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1 902 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659 903 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1 904 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a 905 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1 906 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b 907 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1 908 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c 909 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1 910 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d 911 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1 912 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e 913 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1 914 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f 915 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1 916 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660 917 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1 918 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661 919 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1 920 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662 921 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1 922 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663 923 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1 924 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664 925 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1 926 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665 927 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1 928 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666 929 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1 930 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667 931 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1 932 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668 933 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1 934 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669 935 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1 936 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a 937 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1 938 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b 939 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1 940 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c 941 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1 942 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d 943 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1 944 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e 945 + #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1 946 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f 947 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1 948 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670 949 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1 950 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671 951 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1 952 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672 953 + #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1 954 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673 955 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 956 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674 957 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 958 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675 959 + #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 960 + #define regMMVM_L2_SAW_CNTL 0x0676 961 + #define regMMVM_L2_SAW_CNTL_BASE_IDX 1 962 + #define regMMVM_L2_SAW_CNTL2 0x0677 963 + #define regMMVM_L2_SAW_CNTL2_BASE_IDX 1 964 + #define regMMVM_L2_SAW_CNTL3 0x0678 965 + #define regMMVM_L2_SAW_CNTL3_BASE_IDX 1 966 + #define regMMVM_L2_SAW_CNTL4 0x0679 967 + #define regMMVM_L2_SAW_CNTL4_BASE_IDX 1 968 + #define regMMVM_L2_SAW_CONTEXT0_CNTL 0x067a 969 + #define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 970 + #define regMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b 971 + #define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 972 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c 973 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 974 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d 975 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 976 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e 977 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 978 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f 979 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 980 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680 981 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 982 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681 983 + #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 984 + #define regMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682 985 + #define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 986 + #define regMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683 987 + #define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 988 + #define regMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684 989 + #define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 990 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685 991 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1 992 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686 993 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1 994 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687 995 + #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1 996 + 997 + 998 + // addressBlock: mmhub_mmutcl2_mmatcl2dec 999 + // base address: 0x69b00 1000 + #define regMM_ATC_L2_CNTL 0x06c0 1001 + #define regMM_ATC_L2_CNTL_BASE_IDX 1 1002 + #define regMM_ATC_L2_CNTL2 0x06c1 1003 + #define regMM_ATC_L2_CNTL2_BASE_IDX 1 1004 + #define regMM_ATC_L2_CACHE_DATA0 0x06c4 1005 + #define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 1006 + #define regMM_ATC_L2_CACHE_DATA1 0x06c5 1007 + #define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 1008 + #define regMM_ATC_L2_CACHE_DATA2 0x06c6 1009 + #define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 1010 + #define regMM_ATC_L2_CNTL3 0x06c7 1011 + #define regMM_ATC_L2_CNTL3_BASE_IDX 1 1012 + #define regMM_ATC_L2_CNTL4 0x06c8 1013 + #define regMM_ATC_L2_CNTL4_BASE_IDX 1 1014 + #define regMM_ATC_L2_CNTL5 0x06c9 1015 + #define regMM_ATC_L2_CNTL5_BASE_IDX 1 1016 + #define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca 1017 + #define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1018 + #define regMM_ATC_L2_STATUS 0x06cb 1019 + #define regMM_ATC_L2_STATUS_BASE_IDX 1 1020 + #define regMM_ATC_L2_STATUS2 0x06cc 1021 + #define regMM_ATC_L2_STATUS2_BASE_IDX 1 1022 + #define regMM_ATC_L2_MISC_CG 0x06cd 1023 + #define regMM_ATC_L2_MISC_CG_BASE_IDX 1 1024 + #define regMM_ATC_L2_MEM_POWER_LS 0x06ce 1025 + #define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 1026 + #define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf 1027 + #define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 1028 + #define regMM_ATC_L2_SDPPORT_CTRL 0x06d2 1029 + #define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 1030 + 1031 + 1032 + // addressBlock: mmhub_mmutcl2_mmvml2pfdec 1033 + // base address: 0x69c00 1034 + #define regMMVM_L2_CNTL 0x0700 1035 + #define regMMVM_L2_CNTL_BASE_IDX 1 1036 + #define regMMVM_L2_CNTL2 0x0701 1037 + #define regMMVM_L2_CNTL2_BASE_IDX 1 1038 + #define regMMVM_L2_CNTL3 0x0702 1039 + #define regMMVM_L2_CNTL3_BASE_IDX 1 1040 + #define regMMVM_L2_STATUS 0x0703 1041 + #define regMMVM_L2_STATUS_BASE_IDX 1 1042 + #define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 1043 + #define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 1044 + #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 1045 + #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 1046 + #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 1047 + #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 1048 + #define regMMVM_INVALIDATE_CNTL 0x0707 1049 + #define regMMVM_INVALIDATE_CNTL_BASE_IDX 1 1050 + #define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 1051 + #define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 1052 + #define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 1053 + #define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 1054 + #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a 1055 + #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 1056 + #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b 1057 + #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 1058 + #define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c 1059 + #define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 1060 + #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d 1061 + #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 1062 + #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e 1063 + #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 1064 + #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f 1065 + #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 1066 + #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 1067 + #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 1068 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 1069 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 1070 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 1071 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 1072 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 1073 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 1074 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 1075 + #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 1076 + #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 1077 + #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 1078 + #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 1079 + #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 1080 + #define regMMVM_L2_CNTL4 0x0718 1081 + #define regMMVM_L2_CNTL4_BASE_IDX 1 1082 + #define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 1083 + #define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1084 + #define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a 1085 + #define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 1086 + #define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b 1087 + #define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 1088 + #define regMMVM_L2_CACHE_PARITY_CNTL 0x071c 1089 + #define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 1090 + #define regMMVM_L2_CGTT_CLK_CTRL 0x071d 1091 + #define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 1092 + #define regMMVM_L2_CNTL5 0x071e 1093 + #define regMMVM_L2_CNTL5_BASE_IDX 1 1094 + #define regMMVM_L2_GCR_CNTL 0x071f 1095 + #define regMMVM_L2_GCR_CNTL_BASE_IDX 1 1096 + #define regMMVM_L2_CGTT_BUSY_CTRL 0x0720 1097 + #define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 1098 + #define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721 1099 + #define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 1100 + #define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722 1101 + #define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 1102 + #define regMMVM_L2_BANK_SELECT_MASKS 0x0725 1103 + #define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1 1104 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726 1105 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1 1106 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727 1107 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1 1108 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728 1109 + #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1 1110 + #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729 1111 + #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1 1112 + #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a 1113 + #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 1114 + 1115 + 1116 + // addressBlock: mmhub_mmutcl2_mmvml2vcdec 1117 + // base address: 0x69d00 1118 + #define regMMVM_CONTEXT0_CNTL 0x0740 1119 + #define regMMVM_CONTEXT0_CNTL_BASE_IDX 1 1120 + #define regMMVM_CONTEXT1_CNTL 0x0741 1121 + #define regMMVM_CONTEXT1_CNTL_BASE_IDX 1 1122 + #define regMMVM_CONTEXT2_CNTL 0x0742 1123 + #define regMMVM_CONTEXT2_CNTL_BASE_IDX 1 1124 + #define regMMVM_CONTEXT3_CNTL 0x0743 1125 + #define regMMVM_CONTEXT3_CNTL_BASE_IDX 1 1126 + #define regMMVM_CONTEXT4_CNTL 0x0744 1127 + #define regMMVM_CONTEXT4_CNTL_BASE_IDX 1 1128 + #define regMMVM_CONTEXT5_CNTL 0x0745 1129 + #define regMMVM_CONTEXT5_CNTL_BASE_IDX 1 1130 + #define regMMVM_CONTEXT6_CNTL 0x0746 1131 + #define regMMVM_CONTEXT6_CNTL_BASE_IDX 1 1132 + #define regMMVM_CONTEXT7_CNTL 0x0747 1133 + #define regMMVM_CONTEXT7_CNTL_BASE_IDX 1 1134 + #define regMMVM_CONTEXT8_CNTL 0x0748 1135 + #define regMMVM_CONTEXT8_CNTL_BASE_IDX 1 1136 + #define regMMVM_CONTEXT9_CNTL 0x0749 1137 + #define regMMVM_CONTEXT9_CNTL_BASE_IDX 1 1138 + #define regMMVM_CONTEXT10_CNTL 0x074a 1139 + #define regMMVM_CONTEXT10_CNTL_BASE_IDX 1 1140 + #define regMMVM_CONTEXT11_CNTL 0x074b 1141 + #define regMMVM_CONTEXT11_CNTL_BASE_IDX 1 1142 + #define regMMVM_CONTEXT12_CNTL 0x074c 1143 + #define regMMVM_CONTEXT12_CNTL_BASE_IDX 1 1144 + #define regMMVM_CONTEXT13_CNTL 0x074d 1145 + #define regMMVM_CONTEXT13_CNTL_BASE_IDX 1 1146 + #define regMMVM_CONTEXT14_CNTL 0x074e 1147 + #define regMMVM_CONTEXT14_CNTL_BASE_IDX 1 1148 + #define regMMVM_CONTEXT15_CNTL 0x074f 1149 + #define regMMVM_CONTEXT15_CNTL_BASE_IDX 1 1150 + #define regMMVM_CONTEXTS_DISABLE 0x0750 1151 + #define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1 1152 + #define regMMVM_INVALIDATE_ENG0_SEM 0x0751 1153 + #define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 1154 + #define regMMVM_INVALIDATE_ENG1_SEM 0x0752 1155 + #define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 1156 + #define regMMVM_INVALIDATE_ENG2_SEM 0x0753 1157 + #define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 1158 + #define regMMVM_INVALIDATE_ENG3_SEM 0x0754 1159 + #define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 1160 + #define regMMVM_INVALIDATE_ENG4_SEM 0x0755 1161 + #define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 1162 + #define regMMVM_INVALIDATE_ENG5_SEM 0x0756 1163 + #define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 1164 + #define regMMVM_INVALIDATE_ENG6_SEM 0x0757 1165 + #define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 1166 + #define regMMVM_INVALIDATE_ENG7_SEM 0x0758 1167 + #define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 1168 + #define regMMVM_INVALIDATE_ENG8_SEM 0x0759 1169 + #define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 1170 + #define regMMVM_INVALIDATE_ENG9_SEM 0x075a 1171 + #define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 1172 + #define regMMVM_INVALIDATE_ENG10_SEM 0x075b 1173 + #define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 1174 + #define regMMVM_INVALIDATE_ENG11_SEM 0x075c 1175 + #define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 1176 + #define regMMVM_INVALIDATE_ENG12_SEM 0x075d 1177 + #define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 1178 + #define regMMVM_INVALIDATE_ENG13_SEM 0x075e 1179 + #define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 1180 + #define regMMVM_INVALIDATE_ENG14_SEM 0x075f 1181 + #define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 1182 + #define regMMVM_INVALIDATE_ENG15_SEM 0x0760 1183 + #define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 1184 + #define regMMVM_INVALIDATE_ENG16_SEM 0x0761 1185 + #define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 1186 + #define regMMVM_INVALIDATE_ENG17_SEM 0x0762 1187 + #define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 1188 + #define regMMVM_INVALIDATE_ENG0_REQ 0x0763 1189 + #define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 1190 + #define regMMVM_INVALIDATE_ENG1_REQ 0x0764 1191 + #define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 1192 + #define regMMVM_INVALIDATE_ENG2_REQ 0x0765 1193 + #define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 1194 + #define regMMVM_INVALIDATE_ENG3_REQ 0x0766 1195 + #define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 1196 + #define regMMVM_INVALIDATE_ENG4_REQ 0x0767 1197 + #define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 1198 + #define regMMVM_INVALIDATE_ENG5_REQ 0x0768 1199 + #define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 1200 + #define regMMVM_INVALIDATE_ENG6_REQ 0x0769 1201 + #define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 1202 + #define regMMVM_INVALIDATE_ENG7_REQ 0x076a 1203 + #define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 1204 + #define regMMVM_INVALIDATE_ENG8_REQ 0x076b 1205 + #define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 1206 + #define regMMVM_INVALIDATE_ENG9_REQ 0x076c 1207 + #define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 1208 + #define regMMVM_INVALIDATE_ENG10_REQ 0x076d 1209 + #define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 1210 + #define regMMVM_INVALIDATE_ENG11_REQ 0x076e 1211 + #define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 1212 + #define regMMVM_INVALIDATE_ENG12_REQ 0x076f 1213 + #define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 1214 + #define regMMVM_INVALIDATE_ENG13_REQ 0x0770 1215 + #define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 1216 + #define regMMVM_INVALIDATE_ENG14_REQ 0x0771 1217 + #define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 1218 + #define regMMVM_INVALIDATE_ENG15_REQ 0x0772 1219 + #define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 1220 + #define regMMVM_INVALIDATE_ENG16_REQ 0x0773 1221 + #define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 1222 + #define regMMVM_INVALIDATE_ENG17_REQ 0x0774 1223 + #define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 1224 + #define regMMVM_INVALIDATE_ENG0_ACK 0x0775 1225 + #define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 1226 + #define regMMVM_INVALIDATE_ENG1_ACK 0x0776 1227 + #define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 1228 + #define regMMVM_INVALIDATE_ENG2_ACK 0x0777 1229 + #define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 1230 + #define regMMVM_INVALIDATE_ENG3_ACK 0x0778 1231 + #define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 1232 + #define regMMVM_INVALIDATE_ENG4_ACK 0x0779 1233 + #define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 1234 + #define regMMVM_INVALIDATE_ENG5_ACK 0x077a 1235 + #define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 1236 + #define regMMVM_INVALIDATE_ENG6_ACK 0x077b 1237 + #define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 1238 + #define regMMVM_INVALIDATE_ENG7_ACK 0x077c 1239 + #define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 1240 + #define regMMVM_INVALIDATE_ENG8_ACK 0x077d 1241 + #define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 1242 + #define regMMVM_INVALIDATE_ENG9_ACK 0x077e 1243 + #define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 1244 + #define regMMVM_INVALIDATE_ENG10_ACK 0x077f 1245 + #define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 1246 + #define regMMVM_INVALIDATE_ENG11_ACK 0x0780 1247 + #define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 1248 + #define regMMVM_INVALIDATE_ENG12_ACK 0x0781 1249 + #define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 1250 + #define regMMVM_INVALIDATE_ENG13_ACK 0x0782 1251 + #define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 1252 + #define regMMVM_INVALIDATE_ENG14_ACK 0x0783 1253 + #define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 1254 + #define regMMVM_INVALIDATE_ENG15_ACK 0x0784 1255 + #define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 1256 + #define regMMVM_INVALIDATE_ENG16_ACK 0x0785 1257 + #define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 1258 + #define regMMVM_INVALIDATE_ENG17_ACK 0x0786 1259 + #define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 1260 + #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787 1261 + #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 1262 + #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788 1263 + #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 1264 + #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789 1265 + #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 1266 + #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a 1267 + #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 1268 + #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b 1269 + #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 1270 + #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c 1271 + #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 1272 + #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d 1273 + #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 1274 + #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e 1275 + #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 1276 + #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f 1277 + #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 1278 + #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790 1279 + #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 1280 + #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791 1281 + #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 1282 + #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792 1283 + #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 1284 + #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793 1285 + #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 1286 + #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794 1287 + #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 1288 + #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795 1289 + #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 1290 + #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796 1291 + #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 1292 + #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797 1293 + #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 1294 + #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798 1295 + #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 1296 + #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799 1297 + #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 1298 + #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a 1299 + #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 1300 + #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b 1301 + #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 1302 + #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c 1303 + #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 1304 + #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d 1305 + #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 1306 + #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e 1307 + #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 1308 + #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f 1309 + #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 1310 + #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0 1311 + #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 1312 + #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1 1313 + #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 1314 + #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2 1315 + #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 1316 + #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3 1317 + #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 1318 + #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4 1319 + #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 1320 + #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5 1321 + #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 1322 + #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6 1323 + #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 1324 + #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7 1325 + #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 1326 + #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8 1327 + #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 1328 + #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9 1329 + #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 1330 + #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa 1331 + #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 1332 + #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab 1333 + #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1334 + #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac 1335 + #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1336 + #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad 1337 + #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1338 + #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae 1339 + #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1340 + #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af 1341 + #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1342 + #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0 1343 + #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1344 + #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1 1345 + #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1346 + #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2 1347 + #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1348 + #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3 1349 + #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1350 + #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4 1351 + #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1352 + #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5 1353 + #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1354 + #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6 1355 + #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1356 + #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7 1357 + #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1358 + #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8 1359 + #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1360 + #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9 1361 + #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1362 + #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba 1363 + #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1364 + #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb 1365 + #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1366 + #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc 1367 + #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1368 + #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd 1369 + #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1370 + #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be 1371 + #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1372 + #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf 1373 + #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1374 + #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0 1375 + #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1376 + #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1 1377 + #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1378 + #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2 1379 + #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1380 + #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3 1381 + #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1382 + #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4 1383 + #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1384 + #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5 1385 + #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1386 + #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6 1387 + #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1388 + #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7 1389 + #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1390 + #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8 1391 + #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1392 + #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9 1393 + #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1394 + #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca 1395 + #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1396 + #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb 1397 + #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1398 + #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc 1399 + #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1400 + #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd 1401 + #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1402 + #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce 1403 + #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1404 + #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf 1405 + #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1406 + #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0 1407 + #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1408 + #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1 1409 + #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1410 + #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2 1411 + #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1412 + #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3 1413 + #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1414 + #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4 1415 + #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1416 + #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5 1417 + #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1418 + #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6 1419 + #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1420 + #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7 1421 + #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1422 + #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8 1423 + #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1424 + #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9 1425 + #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1426 + #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da 1427 + #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1428 + #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db 1429 + #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1430 + #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc 1431 + #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1432 + #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd 1433 + #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1434 + #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de 1435 + #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1436 + #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df 1437 + #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1438 + #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0 1439 + #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1440 + #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1 1441 + #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1442 + #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2 1443 + #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1444 + #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3 1445 + #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1446 + #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4 1447 + #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1448 + #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5 1449 + #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1450 + #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6 1451 + #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1452 + #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7 1453 + #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1454 + #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8 1455 + #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1456 + #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9 1457 + #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1458 + #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea 1459 + #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1460 + #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb 1461 + #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1462 + #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec 1463 + #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1464 + #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed 1465 + #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1466 + #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee 1467 + #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1468 + #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef 1469 + #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1470 + #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0 1471 + #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1472 + #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1 1473 + #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1474 + #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2 1475 + #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1476 + #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3 1477 + #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1478 + #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4 1479 + #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1480 + #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5 1481 + #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1482 + #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6 1483 + #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1484 + #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7 1485 + #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1486 + #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8 1487 + #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1488 + #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9 1489 + #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1490 + #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa 1491 + #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1492 + #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb 1493 + #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1494 + #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc 1495 + #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1496 + #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd 1497 + #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1498 + #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe 1499 + #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1500 + #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff 1501 + #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1502 + #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800 1503 + #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1504 + #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801 1505 + #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1506 + #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802 1507 + #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1508 + #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803 1509 + #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1510 + #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804 1511 + #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1512 + #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805 1513 + #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1514 + #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806 1515 + #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1516 + #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807 1517 + #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1518 + #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808 1519 + #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1520 + #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809 1521 + #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1522 + #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a 1523 + #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1524 + #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b 1525 + #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1526 + #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c 1527 + #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1528 + #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d 1529 + #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1530 + #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e 1531 + #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1532 + #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f 1533 + #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1534 + #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810 1535 + #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1536 + #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811 1537 + #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1538 + #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812 1539 + #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1540 + #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813 1541 + #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1542 + #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814 1543 + #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1544 + #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815 1545 + #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1546 + #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816 1547 + #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1548 + #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817 1549 + #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1550 + #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818 1551 + #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1552 + #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819 1553 + #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1554 + #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a 1555 + #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1556 + #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b 1557 + #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1558 + 1559 + 1560 + // addressBlock: mmhub_mmutcl2_mmvml2pldec 1561 + // base address: 0x6a090 1562 + #define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 1563 + #define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1564 + #define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 1565 + #define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1566 + #define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 1567 + #define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 1568 + #define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 1569 + #define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 1570 + #define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 1571 + #define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 1572 + #define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 1573 + #define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 1574 + #define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a 1575 + #define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 1576 + #define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b 1577 + #define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 1578 + #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c 1579 + #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1580 + #define regMMUTCL2_PERFCOUNTER0_CFG 0x082d 1581 + #define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 1582 + #define regMMUTCL2_PERFCOUNTER1_CFG 0x082e 1583 + #define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 1584 + #define regMMUTCL2_PERFCOUNTER2_CFG 0x082f 1585 + #define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 1586 + #define regMMUTCL2_PERFCOUNTER3_CFG 0x0830 1587 + #define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 1588 + #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 1589 + #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1590 + 1591 + 1592 + // addressBlock: mmhub_mmutcl2_mmvml2prdec 1593 + // base address: 0x6a0e0 1594 + #define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838 1595 + #define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 1596 + #define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839 1597 + #define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 1598 + #define regMMUTCL2_PERFCOUNTER_LO 0x083a 1599 + #define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 1600 + #define regMMUTCL2_PERFCOUNTER_HI 0x083b 1601 + #define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 1602 + 1603 + 1604 + // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1605 + // base address: 0x6a130 1606 + #define regMMVM_PCIE_ATS_CNTL 0x084c 1607 + #define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1 1608 + 1609 + 1610 + // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1611 + // base address: 0x6a340 1612 + #define regMMMC_VM_NB_MMIOBASE 0x08d0 1613 + #define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1 1614 + #define regMMMC_VM_NB_MMIOLIMIT 0x08d1 1615 + #define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 1616 + #define regMMMC_VM_NB_PCI_CTRL 0x08d2 1617 + #define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 1618 + #define regMMMC_VM_NB_PCI_ARB 0x08d3 1619 + #define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1 1620 + #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4 1621 + #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 1622 + #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5 1623 + #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 1624 + #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6 1625 + #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 1626 + #define regMMMC_VM_FB_OFFSET 0x08d7 1627 + #define regMMMC_VM_FB_OFFSET_BASE_IDX 1 1628 + #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 1629 + #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 1630 + #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 1631 + #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 1632 + #define regMMMC_VM_STEERING 0x08da 1633 + #define regMMMC_VM_STEERING_BASE_IDX 1 1634 + #define regMMMC_SHARED_VIRT_RESET_REQ 0x08db 1635 + #define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 1636 + #define regMMMC_MEM_POWER_LS 0x08dc 1637 + #define regMMMC_MEM_POWER_LS_BASE_IDX 1 1638 + #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd 1639 + #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 1640 + #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de 1641 + #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 1642 + #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df 1643 + #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 1644 + #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0 1645 + #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 1646 + #define regMMMC_VM_APT_CNTL 0x08e1 1647 + #define regMMMC_VM_APT_CNTL_BASE_IDX 1 1648 + #define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2 1649 + #define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 1650 + #define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3 1651 + #define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 1652 + #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4 1653 + #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 1654 + #define regMMUTCL2_CGTT_CLK_CTRL 0x08e5 1655 + #define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 1656 + #define regMMMC_SHARED_ACTIVE_FCN_ID 0x08e6 1657 + #define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 1658 + #define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7 1659 + #define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 1660 + #define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e8 1661 + #define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 1662 + #define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08ea 1663 + #define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1 1664 + 1665 + 1666 + // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1667 + // base address: 0x6a3b0 1668 + #define regMMMC_VM_FB_LOCATION_BASE 0x08ec 1669 + #define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 1670 + #define regMMMC_VM_FB_LOCATION_TOP 0x08ed 1671 + #define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 1672 + #define regMMMC_VM_AGP_TOP 0x08ee 1673 + #define regMMMC_VM_AGP_TOP_BASE_IDX 1 1674 + #define regMMMC_VM_AGP_BOT 0x08ef 1675 + #define regMMMC_VM_AGP_BOT_BASE_IDX 1 1676 + #define regMMMC_VM_AGP_BASE 0x08f0 1677 + #define regMMMC_VM_AGP_BASE_BASE_IDX 1 1678 + #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 1679 + #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 1680 + #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 1681 + #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 1682 + #define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3 1683 + #define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 1684 + 1685 + 1686 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1687 + // base address: 0x6a400 1688 + #define regMM_ATC_L2_PERFCOUNTER_LO 0x0900 1689 + #define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 1690 + #define regMM_ATC_L2_PERFCOUNTER_HI 0x0901 1691 + #define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 1692 + 1693 + 1694 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1695 + // base address: 0x6a420 1696 + #define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 1697 + #define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1698 + #define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 1699 + #define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1700 + #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a 1701 + #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1702 + 1703 + 1704 + // addressBlock: mmhub_mmutcl2_mmvml2pspdec 1705 + // base address: 0x6aa50 1706 + #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94 1707 + #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 1708 + #define regMMVM_IOMMU_CONTROL_REGISTER 0x0a97 1709 + #define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 1710 + #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0a98 1711 + #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 1712 + #define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99 1713 + #define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 1714 + #define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a 1715 + #define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 1716 + 1717 + 1718 + // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 1719 + // base address: 0x6aa80 1720 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0 1721 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 1722 + 1723 + 1724 + // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 1725 + // base address: 0x6aa90 1726 + #define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4 1727 + #define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 1 1728 + 1729 + 1730 + // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 1731 + // base address: 0x6aac0 1732 + #define regMML2TLB_TLB0_STATUS 0x0ab1 1733 + #define regMML2TLB_TLB0_STATUS_BASE_IDX 1 1734 + #define regMML2TLB_TMZ_CNTL 0x0ab2 1735 + #define regMML2TLB_TMZ_CNTL_BASE_IDX 1 1736 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3 1737 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1 1738 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4 1739 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1 1740 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5 1741 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1 1742 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6 1743 + #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1 1744 + #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7 1745 + #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 1746 + 1747 + 1748 + // addressBlock: mmhub_mmutcl2_mml2tlbpldec 1749 + // base address: 0x6ab00 1750 + #define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0 1751 + #define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 1752 + #define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1 1753 + #define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 1754 + #define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2 1755 + #define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 1756 + #define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3 1757 + #define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 1758 + #define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 1759 + #define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1760 + 1761 + 1762 + // addressBlock: mmhub_mmutcl2_mml2tlbprdec 1763 + // base address: 0x6ab20 1764 + #define regMML2TLB_PERFCOUNTER_LO 0x0ac8 1765 + #define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 1766 + #define regMML2TLB_PERFCOUNTER_HI 0x0ac9 1767 + #define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 1768 + 1769 + #endif
+7483
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _mmhub_3_0_1_SH_MASK_HEADER 24 + #define _mmhub_3_0_1_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: mmhub_dagbdec 28 + //DAGB0_RDCLI0 29 + #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 + #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 + #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 + #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 + #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 + #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 + #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 + #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 + #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 + #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 + #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 + #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 + #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 + #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 + #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 + #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 + #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 + #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 + #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 + #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 + //DAGB0_RDCLI1 50 + #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 + #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 + #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 + #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 + #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 + #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 + #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 + #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 + #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 + #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 + #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 + #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 + #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 + #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 + #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 + #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 + #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 + #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 + #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 + #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 + //DAGB0_RDCLI2 71 + #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 + #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 + #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 + #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 + #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 + #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 + #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 + #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 + #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 + #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 + #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 + #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 + #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 + #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 + #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 + #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 + #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 + #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 + #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 + #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 + //DAGB0_RDCLI3 92 + #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 + #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 + #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 + #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 + #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 + #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 + #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 + #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 + #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 + #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 + #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 + #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 + #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 + #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 + #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 + #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 + #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 + #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 + #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 + #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 + //DAGB0_RDCLI4 113 + #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 + #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 + #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 + #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 + #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 + #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 + #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 + #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 + #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 + #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 + #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 + #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 + #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 + #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 + #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 + #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 + #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 + #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 + #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 + #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 + //DAGB0_RDCLI5 134 + #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 + #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 + #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 + #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 + #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 + #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 + #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 + #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 + #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 + #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 + #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 + #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 + #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 + #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 + #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 + #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 + #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 + #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 + #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 + #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 + //DAGB0_RDCLI6 155 + #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 + #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 + #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 + #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 + #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 + #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 + #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 + #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 + #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 + #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 + #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 + #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 + #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 + #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 + #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 + #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 + #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 + #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 + #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 + #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 + //DAGB0_RDCLI7 176 + #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 + #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 + #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 + #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 + #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 + #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 + #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 + #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 + #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 + #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 + #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 + #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 + #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 + #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 + #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 + #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 + #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 + #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 + #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 + #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 + //DAGB0_RDCLI8 197 + #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 + #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 + #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 + #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 + #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 + #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 + #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 + #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 + #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 + #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 + #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 + #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 + #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 + #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 + #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 + #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 + #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 + #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 + #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 + #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 + //DAGB0_RDCLI9 218 + #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 + #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 + #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 + #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 + #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 + #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 + #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 + #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 + #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 + #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 + #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 + #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 + #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 + #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 + #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 + #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 + #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 + #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 + #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 + #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 + //DAGB0_RDCLI10 239 + #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 + #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 + #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 + #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 + #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 + #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 + #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 + #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 + #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 + #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 + #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 + #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 + #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 + #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 + #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 + #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 + #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 + #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 + #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 + #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 + //DAGB0_RDCLI11 260 + #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 + #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 + #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 + #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 + #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 + #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 + #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 + #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 + #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 + #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 + #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 + #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 + #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 + #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 + #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 + #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 + #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 + #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 + #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 + #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 + //DAGB0_RDCLI12 281 + #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 + #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 + #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 + #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 + #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 + #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 + #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 + #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 + #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 + #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 + #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 + #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 + #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 + #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 + #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 + #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 + #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 + #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 + #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 + #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 + //DAGB0_RDCLI13 302 + #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 + #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 + #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 + #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 + #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 + #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 + #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 + #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 + #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 + #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 + #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 + #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 + #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 + #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 + #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 + #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 + #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 + #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 + #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 + #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 + //DAGB0_RDCLI14 323 + #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 + #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 + #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 + #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 + #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 + #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 + #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 + #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 + #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 + #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 + #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 + #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 + #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 + #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 + #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 + #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 + #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 + #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 + #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 + #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 + //DAGB0_RDCLI15 344 + #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 + #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 + #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 + #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 + #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 + #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 + #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 + #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 + #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 + #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 + #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 + #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 + #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 + #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 + #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 + #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 + #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 + #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 + #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 + #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 + //DAGB0_RDCLI16 365 + #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366 + #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367 + #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368 + #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369 + #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370 + #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371 + #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372 + #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373 + #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374 + #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375 + #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376 + #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377 + #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378 + #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379 + #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380 + #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381 + #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382 + #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383 + #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384 + #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385 + //DAGB0_RDCLI17 386 + #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387 + #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388 + #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389 + #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390 + #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391 + #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392 + #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393 + #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394 + #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395 + #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396 + #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397 + #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398 + #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399 + #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400 + #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401 + #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402 + #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403 + #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404 + #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405 + #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406 + //DAGB0_RDCLI18 407 + #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408 + #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409 + #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410 + #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411 + #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412 + #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413 + #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414 + #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415 + #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416 + #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417 + #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418 + #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419 + #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420 + #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421 + #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422 + #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423 + #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424 + #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425 + #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426 + #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427 + //DAGB0_RDCLI19 428 + #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429 + #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430 + #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431 + #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432 + #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433 + #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434 + #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435 + #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436 + #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437 + #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438 + #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439 + #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440 + #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441 + #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442 + #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443 + #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444 + #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445 + #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446 + #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447 + #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448 + //DAGB0_RDCLI20 449 + #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450 + #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451 + #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452 + #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453 + #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454 + #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455 + #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456 + #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457 + #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458 + #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459 + #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460 + #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461 + #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462 + #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463 + #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464 + #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465 + #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466 + #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467 + #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468 + #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469 + //DAGB0_RDCLI21 470 + #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471 + #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472 + #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473 + #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474 + #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475 + #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476 + #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477 + #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478 + #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479 + #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480 + #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481 + #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482 + #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483 + #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484 + #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485 + #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486 + #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487 + #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488 + #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489 + #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490 + //DAGB0_RDCLI22 491 + #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492 + #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493 + #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494 + #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495 + #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496 + #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497 + #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498 + #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499 + #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500 + #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501 + #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502 + #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503 + #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504 + #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505 + #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506 + #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507 + #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508 + #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509 + #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510 + #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511 + //DAGB0_RDCLI23 512 + #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513 + #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514 + #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515 + #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516 + #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517 + #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518 + #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519 + #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520 + #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521 + #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522 + #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523 + #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524 + #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525 + #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526 + #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527 + #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528 + #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529 + #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530 + #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531 + #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532 + //DAGB0_RDCLI24 533 + #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 534 + #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 535 + #define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 536 + #define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 537 + #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc 538 + #define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd 539 + #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 540 + #define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 541 + #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 542 + #define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a 543 + #define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L 544 + #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 545 + #define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L 546 + #define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L 547 + #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L 548 + #define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L 549 + #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L 550 + #define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L 551 + #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 552 + #define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L 553 + //DAGB0_RDCLI25 554 + #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 555 + #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 556 + #define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 557 + #define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 558 + #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc 559 + #define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd 560 + #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 561 + #define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 562 + #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 563 + #define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a 564 + #define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L 565 + #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 566 + #define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L 567 + #define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L 568 + #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L 569 + #define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L 570 + #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L 571 + #define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L 572 + #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 573 + #define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L 574 + //DAGB0_RDCLI26 575 + #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 576 + #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 577 + #define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 578 + #define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 579 + #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc 580 + #define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd 581 + #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 582 + #define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 583 + #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 584 + #define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a 585 + #define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L 586 + #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 587 + #define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L 588 + #define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L 589 + #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L 590 + #define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L 591 + #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L 592 + #define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L 593 + #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 594 + #define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L 595 + //DAGB0_RDCLI27 596 + #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 597 + #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 598 + #define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 599 + #define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 600 + #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc 601 + #define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd 602 + #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 603 + #define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 604 + #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 605 + #define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a 606 + #define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L 607 + #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 608 + #define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L 609 + #define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L 610 + #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L 611 + #define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L 612 + #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L 613 + #define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L 614 + #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 615 + #define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L 616 + //DAGB0_RDCLI28 617 + #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 618 + #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 619 + #define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 620 + #define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 621 + #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc 622 + #define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd 623 + #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 624 + #define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 625 + #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 626 + #define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a 627 + #define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L 628 + #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 629 + #define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L 630 + #define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L 631 + #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L 632 + #define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L 633 + #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L 634 + #define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L 635 + #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 636 + #define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L 637 + //DAGB0_RDCLI29 638 + #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 639 + #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 640 + #define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 641 + #define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 642 + #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc 643 + #define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd 644 + #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 645 + #define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 646 + #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 647 + #define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a 648 + #define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L 649 + #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 650 + #define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L 651 + #define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L 652 + #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L 653 + #define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L 654 + #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L 655 + #define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L 656 + #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 657 + #define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L 658 + //DAGB0_RD_CNTL 659 + #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 660 + #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 661 + #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 662 + #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 663 + #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 664 + #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 665 + #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 666 + #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 667 + //DAGB0_RD_IO_CNTL 668 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 669 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 670 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 671 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 672 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 673 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 674 + #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 675 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 676 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 677 + #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 678 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 679 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 680 + #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 681 + #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 682 + //DAGB0_RD_GMI_CNTL 683 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 684 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 685 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 686 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 687 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 688 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 689 + #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 690 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 691 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 692 + #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 693 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 694 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 695 + #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 696 + #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 697 + //DAGB0_RD_ADDR_DAGB 698 + #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 699 + #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 700 + #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 701 + #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 702 + #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 703 + #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 704 + #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 705 + #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 706 + #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 707 + #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 708 + //DAGB0_RD_CGTT_CLK_CTRL 709 + #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 710 + #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 711 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 712 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 713 + #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 714 + #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 715 + #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 716 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 717 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 718 + #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 719 + //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 720 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 721 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 722 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 723 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 724 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 725 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 726 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 727 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 728 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 729 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 730 + //DAGB0_RD_ADDR_DAGB_MAX_BURST0 731 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 732 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 733 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 734 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 735 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 736 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 737 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 738 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 739 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 740 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 741 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 742 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 743 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 744 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 745 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 746 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 747 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 748 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 749 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 750 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 751 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 752 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 753 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 754 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 755 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 756 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 757 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 758 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 759 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 760 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 761 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 762 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 763 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 764 + //DAGB0_RD_ADDR_DAGB_MAX_BURST1 765 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 766 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 767 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 768 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 769 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 770 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 771 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 772 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 773 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 774 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 775 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 776 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 777 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 778 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 779 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 780 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 781 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 782 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 783 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 784 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 785 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 786 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 787 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 788 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 789 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 790 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 791 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 792 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 793 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 794 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 795 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 796 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 797 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 798 + //DAGB0_RD_ADDR_DAGB_MAX_BURST2 799 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 800 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 801 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 802 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 803 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 804 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 805 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 806 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 807 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 808 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 809 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 810 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 811 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 812 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 813 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 814 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 815 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 816 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 817 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 818 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 819 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 820 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 821 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 822 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 823 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 824 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 825 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 826 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 827 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 828 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 829 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 830 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 831 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 832 + //DAGB0_RD_ADDR_DAGB_MAX_BURST3 833 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 834 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 835 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 836 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 837 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 838 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 839 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 840 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 841 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 842 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 843 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 844 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 845 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 846 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 847 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 848 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 849 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 850 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 851 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 852 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 853 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 854 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 855 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 856 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 857 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 858 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 859 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 860 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 861 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 862 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 863 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 864 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 865 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 866 + //DAGB0_RD_VC0_CNTL 867 + #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 868 + #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 869 + #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 870 + #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 871 + #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 872 + #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 873 + #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 874 + #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 875 + #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 876 + #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 877 + #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 878 + #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 879 + #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 880 + #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 881 + //DAGB0_RD_VC1_CNTL 882 + #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 883 + #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 884 + #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 885 + #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 886 + #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 887 + #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 888 + #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 889 + #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 890 + #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 891 + #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 892 + #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 893 + #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 894 + #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 895 + #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 896 + //DAGB0_RD_VC2_CNTL 897 + #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 898 + #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 899 + #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 900 + #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 901 + #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 902 + #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 903 + #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 904 + #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 905 + #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 906 + #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 907 + #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 908 + #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 909 + #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 910 + #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 911 + //DAGB0_RD_VC3_CNTL 912 + #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 913 + #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 914 + #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 915 + #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 916 + #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 917 + #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 918 + #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 919 + #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 920 + #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 921 + #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 922 + #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 923 + #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 924 + #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 925 + #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 926 + //DAGB0_RD_VC4_CNTL 927 + #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 928 + #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 929 + #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 930 + #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 931 + #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 932 + #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 933 + #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 934 + #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 935 + #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 936 + #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 937 + #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 938 + #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 939 + #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 940 + #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 941 + //DAGB0_RD_VC5_CNTL 942 + #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 943 + #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 944 + #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 945 + #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 946 + #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 947 + #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 948 + #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 949 + #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 950 + #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 951 + #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 952 + #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 953 + #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 954 + #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 955 + #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 956 + //DAGB0_RD_IO_VC_CNTL 957 + #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 958 + #define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 959 + #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 960 + #define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 961 + #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 962 + #define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 963 + #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 964 + #define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 965 + #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 966 + #define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 967 + #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 968 + #define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 969 + //DAGB0_RD_GMI_VC_CNTL 970 + #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 971 + #define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 972 + #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 973 + #define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 974 + #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 975 + #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 976 + #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 977 + #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 978 + #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 979 + #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 980 + #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 981 + #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 982 + //DAGB0_RD_CNTL_MISC 983 + #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 984 + #define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 985 + #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 986 + #define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 987 + //DAGB0_RD_TLB_CREDIT 988 + #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 989 + #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 990 + #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 991 + #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 992 + #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 993 + #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 994 + #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 995 + #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 996 + #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 997 + #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 998 + #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 999 + #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 1000 + //DAGB0_RDCLI_ASK_PENDING 1001 + #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 1002 + #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1003 + //DAGB0_RDCLI_GO_PENDING 1004 + #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 1005 + #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1006 + //DAGB0_RDCLI_GBLSEND_PENDING 1007 + #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1008 + #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1009 + //DAGB0_RDCLI_TLB_PENDING 1010 + #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 1011 + #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1012 + //DAGB0_RDCLI_OARB_PENDING 1013 + #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 1014 + #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1015 + //DAGB0_RDCLI_ASK2ARB_PENDING 1016 + #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 1017 + #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1018 + //DAGB0_RDCLI_ASK2DF_PENDING 1019 + #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 1020 + #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 1021 + //DAGB0_RDCLI_OSD_PENDING 1022 + #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 1023 + #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1024 + //DAGB0_RDCLI_ASK_OSD_PENDING 1025 + #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 1026 + #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1027 + //DAGB0_WRCLI0 1028 + #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 1029 + #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1030 + #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 1031 + #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 1032 + #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 1033 + #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 1034 + #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 1035 + #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 1036 + #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1037 + #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 1038 + #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 1039 + #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1040 + #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 1041 + #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 1042 + #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1043 + #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 1044 + #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1045 + #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 1046 + #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1047 + #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 1048 + //DAGB0_WRCLI1 1049 + #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 1050 + #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1051 + #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 1052 + #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 1053 + #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 1054 + #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 1055 + #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 1056 + #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 1057 + #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1058 + #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 1059 + #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 1060 + #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1061 + #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 1062 + #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 1063 + #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1064 + #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 1065 + #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1066 + #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 1067 + #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1068 + #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 1069 + //DAGB0_WRCLI2 1070 + #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 1071 + #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1072 + #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 1073 + #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 1074 + #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 1075 + #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 1076 + #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 1077 + #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 1078 + #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1079 + #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 1080 + #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 1081 + #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1082 + #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 1083 + #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 1084 + #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1085 + #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 1086 + #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1087 + #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 1088 + #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1089 + #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 1090 + //DAGB0_WRCLI3 1091 + #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 1092 + #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1093 + #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 1094 + #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 1095 + #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 1096 + #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 1097 + #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 1098 + #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 1099 + #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1100 + #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 1101 + #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 1102 + #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1103 + #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 1104 + #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 1105 + #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1106 + #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 1107 + #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1108 + #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 1109 + #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1110 + #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 1111 + //DAGB0_WRCLI4 1112 + #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 1113 + #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1114 + #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 1115 + #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 1116 + #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 1117 + #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 1118 + #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 1119 + #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 1120 + #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1121 + #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 1122 + #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 1123 + #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1124 + #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 1125 + #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 1126 + #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1127 + #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 1128 + #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1129 + #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 1130 + #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1131 + #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1132 + //DAGB0_WRCLI5 1133 + #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1134 + #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1135 + #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1136 + #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1137 + #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1138 + #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1139 + #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1140 + #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1141 + #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1142 + #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1143 + #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1144 + #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1145 + #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1146 + #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1147 + #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1148 + #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1149 + #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1150 + #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1151 + #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1152 + #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1153 + //DAGB0_WRCLI6 1154 + #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1155 + #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1156 + #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1157 + #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1158 + #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1159 + #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1160 + #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1161 + #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1162 + #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1163 + #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1164 + #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1165 + #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1166 + #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1167 + #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1168 + #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1169 + #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1170 + #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1171 + #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1172 + #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1173 + #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1174 + //DAGB0_WRCLI7 1175 + #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1176 + #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1177 + #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1178 + #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1179 + #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1180 + #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1181 + #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1182 + #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1183 + #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1184 + #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1185 + #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1186 + #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1187 + #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1188 + #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1189 + #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1190 + #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1191 + #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1192 + #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1193 + #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1194 + #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1195 + //DAGB0_WRCLI8 1196 + #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1197 + #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1198 + #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1199 + #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1200 + #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1201 + #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1202 + #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1203 + #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1204 + #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1205 + #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1206 + #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1207 + #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1208 + #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1209 + #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1210 + #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1211 + #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1212 + #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1213 + #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1214 + #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1215 + #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1216 + //DAGB0_WRCLI9 1217 + #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1218 + #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1219 + #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1220 + #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1221 + #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1222 + #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1223 + #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1224 + #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1225 + #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1226 + #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1227 + #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1228 + #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1229 + #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1230 + #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1231 + #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1232 + #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1233 + #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1234 + #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1235 + #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1236 + #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1237 + //DAGB0_WRCLI10 1238 + #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1239 + #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1240 + #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1241 + #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1242 + #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1243 + #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1244 + #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1245 + #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1246 + #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1247 + #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1248 + #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1249 + #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1250 + #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1251 + #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1252 + #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1253 + #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1254 + #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1255 + #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1256 + #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1257 + #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1258 + //DAGB0_WRCLI11 1259 + #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1260 + #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1261 + #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1262 + #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1263 + #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1264 + #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1265 + #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1266 + #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1267 + #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1268 + #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1269 + #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1270 + #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1271 + #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1272 + #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1273 + #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1274 + #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1275 + #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1276 + #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1277 + #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1278 + #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1279 + //DAGB0_WRCLI12 1280 + #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1281 + #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1282 + #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1283 + #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1284 + #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1285 + #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1286 + #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1287 + #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1288 + #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1289 + #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1290 + #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1291 + #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1292 + #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1293 + #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1294 + #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1295 + #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1296 + #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1297 + #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1298 + #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1299 + #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1300 + //DAGB0_WRCLI13 1301 + #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1302 + #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1303 + #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1304 + #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1305 + #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1306 + #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1307 + #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1308 + #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1309 + #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1310 + #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1311 + #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1312 + #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1313 + #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1314 + #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1315 + #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1316 + #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1317 + #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1318 + #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1319 + #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1320 + #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1321 + //DAGB0_WRCLI14 1322 + #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1323 + #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1324 + #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1325 + #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1326 + #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1327 + #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1328 + #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1329 + #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1330 + #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1331 + #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1332 + #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1333 + #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1334 + #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1335 + #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1336 + #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1337 + #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1338 + #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1339 + #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1340 + #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1341 + #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1342 + //DAGB0_WRCLI15 1343 + #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1344 + #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1345 + #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1346 + #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1347 + #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1348 + #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1349 + #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1350 + #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1351 + #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1352 + #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1353 + #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1354 + #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1355 + #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1356 + #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1357 + #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1358 + #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1359 + #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1360 + #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1361 + #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1362 + #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1363 + //DAGB0_WRCLI16 1364 + #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1365 + #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1366 + #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1367 + #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1368 + #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1369 + #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1370 + #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1371 + #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1372 + #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1373 + #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1374 + #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1375 + #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1376 + #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1377 + #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1378 + #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1379 + #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1380 + #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1381 + #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1382 + #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1383 + #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1384 + //DAGB0_WRCLI17 1385 + #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1386 + #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1387 + #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1388 + #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1389 + #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1390 + #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1391 + #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1392 + #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1393 + #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1394 + #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1395 + #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1396 + #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1397 + #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1398 + #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1399 + #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1400 + #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1401 + #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1402 + #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1403 + #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1404 + #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1405 + //DAGB0_WRCLI18 1406 + #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1407 + #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1408 + #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1409 + #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1410 + #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1411 + #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1412 + #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1413 + #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1414 + #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1415 + #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1416 + #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1417 + #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1418 + #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1419 + #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1420 + #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1421 + #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1422 + #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1423 + #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1424 + #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1425 + #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1426 + //DAGB0_WRCLI19 1427 + #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1428 + #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1429 + #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1430 + #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1431 + #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1432 + #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1433 + #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1434 + #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1435 + #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1436 + #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1437 + #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1438 + #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1439 + #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1440 + #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1441 + #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1442 + #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1443 + #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1444 + #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1445 + #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1446 + #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1447 + //DAGB0_WRCLI20 1448 + #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1449 + #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1450 + #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1451 + #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1452 + #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1453 + #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1454 + #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1455 + #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1456 + #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1457 + #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1458 + #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1459 + #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1460 + #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1461 + #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1462 + #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1463 + #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1464 + #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1465 + #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1466 + #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1467 + #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1468 + //DAGB0_WRCLI21 1469 + #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1470 + #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1471 + #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1472 + #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1473 + #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1474 + #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1475 + #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1476 + #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1477 + #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1478 + #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1479 + #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1480 + #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1481 + #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1482 + #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1483 + #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1484 + #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1485 + #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1486 + #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1487 + #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1488 + #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1489 + //DAGB0_WRCLI22 1490 + #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1491 + #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1492 + #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1493 + #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1494 + #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1495 + #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1496 + #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1497 + #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1498 + #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1499 + #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1500 + #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1501 + #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1502 + #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1503 + #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1504 + #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1505 + #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1506 + #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1507 + #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1508 + #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1509 + #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1510 + //DAGB0_WRCLI23 1511 + #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1512 + #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1513 + #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1514 + #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1515 + #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1516 + #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1517 + #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1518 + #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1519 + #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1520 + #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1521 + #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1522 + #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1523 + #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1524 + #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1525 + #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1526 + #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1527 + #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1528 + #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1529 + #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1530 + #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1531 + //DAGB0_WRCLI24 1532 + #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 1533 + #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 1534 + #define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 1535 + #define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 1536 + #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc 1537 + #define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd 1538 + #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 1539 + #define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 1540 + #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 1541 + #define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a 1542 + #define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L 1543 + #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 1544 + #define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L 1545 + #define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L 1546 + #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L 1547 + #define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L 1548 + #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L 1549 + #define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L 1550 + #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 1551 + #define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L 1552 + //DAGB0_WRCLI25 1553 + #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 1554 + #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 1555 + #define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 1556 + #define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 1557 + #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc 1558 + #define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd 1559 + #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 1560 + #define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 1561 + #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 1562 + #define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a 1563 + #define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L 1564 + #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 1565 + #define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L 1566 + #define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L 1567 + #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L 1568 + #define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L 1569 + #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L 1570 + #define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L 1571 + #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 1572 + #define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L 1573 + //DAGB0_WRCLI26 1574 + #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 1575 + #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 1576 + #define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 1577 + #define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 1578 + #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc 1579 + #define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd 1580 + #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 1581 + #define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 1582 + #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 1583 + #define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a 1584 + #define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L 1585 + #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 1586 + #define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L 1587 + #define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L 1588 + #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L 1589 + #define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L 1590 + #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L 1591 + #define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L 1592 + #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 1593 + #define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L 1594 + //DAGB0_WRCLI27 1595 + #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 1596 + #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 1597 + #define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 1598 + #define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 1599 + #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc 1600 + #define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd 1601 + #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 1602 + #define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 1603 + #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 1604 + #define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a 1605 + #define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L 1606 + #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 1607 + #define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L 1608 + #define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L 1609 + #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L 1610 + #define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L 1611 + #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L 1612 + #define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L 1613 + #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 1614 + #define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L 1615 + //DAGB0_WRCLI28 1616 + #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 1617 + #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 1618 + #define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 1619 + #define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 1620 + #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc 1621 + #define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd 1622 + #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 1623 + #define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 1624 + #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 1625 + #define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a 1626 + #define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L 1627 + #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 1628 + #define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L 1629 + #define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L 1630 + #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L 1631 + #define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L 1632 + #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L 1633 + #define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L 1634 + #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 1635 + #define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L 1636 + //DAGB0_WRCLI29 1637 + #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 1638 + #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 1639 + #define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 1640 + #define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 1641 + #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc 1642 + #define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd 1643 + #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 1644 + #define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 1645 + #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 1646 + #define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a 1647 + #define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L 1648 + #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 1649 + #define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L 1650 + #define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L 1651 + #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L 1652 + #define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L 1653 + #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L 1654 + #define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L 1655 + #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 1656 + #define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L 1657 + //DAGB0_WR_CNTL 1658 + #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 1659 + #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 1660 + #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc 1661 + #define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd 1662 + #define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe 1663 + #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 1664 + #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 1665 + #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L 1666 + #define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L 1667 + #define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L 1668 + //DAGB0_WR_IO_CNTL 1669 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1670 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1671 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1672 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1673 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1674 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1675 + #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 1676 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1677 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1678 + #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1679 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1680 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1681 + #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1682 + #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1683 + //DAGB0_WR_GMI_CNTL 1684 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1685 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1686 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1687 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1688 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1689 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1690 + #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 1691 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1692 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1693 + #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1694 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1695 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1696 + #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1697 + #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1698 + //DAGB0_WR_ADDR_DAGB 1699 + #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1700 + #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1701 + #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1702 + #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1703 + #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1704 + #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1705 + #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1706 + #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1707 + #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1708 + #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1709 + //DAGB0_WR_CGTT_CLK_CTRL 1710 + #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1711 + #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1712 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1713 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1714 + #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1715 + #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1716 + #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1717 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1718 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1719 + #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1720 + //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1721 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1722 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1723 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1724 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1725 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1726 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1727 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1728 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1729 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1730 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1731 + //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1732 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1733 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1734 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1735 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1736 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1737 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1738 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1739 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1740 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1741 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1742 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1743 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1744 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1745 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1746 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1747 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1748 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1749 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1750 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1751 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1752 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1753 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1754 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1755 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1756 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1757 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1758 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1759 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1760 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1761 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1762 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1763 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1764 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1765 + //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1766 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1767 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1768 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1769 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1770 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1771 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1772 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1773 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1774 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1775 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1776 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1777 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1778 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1779 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1780 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1781 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1782 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1783 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1784 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1785 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1786 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1787 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1788 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1789 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1790 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1791 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1792 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1793 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1794 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1795 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1796 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1797 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1798 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1799 + //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1800 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1801 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1802 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1803 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1804 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1805 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1806 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1807 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1808 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1809 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1810 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1811 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1812 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1813 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1814 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1815 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1816 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1817 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1818 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1819 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1820 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1821 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1822 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1823 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1824 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1825 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1826 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1827 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1828 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1829 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1830 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1831 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1832 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1833 + //DAGB0_WR_ADDR_DAGB_MAX_BURST3 1834 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 1835 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 1836 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 1837 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 1838 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 1839 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 1840 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 1841 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 1842 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 1843 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 1844 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 1845 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 1846 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 1847 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 1848 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 1849 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 1850 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 1851 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 1852 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 1853 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 1854 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 1855 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 1856 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 1857 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 1858 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 1859 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 1860 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 1861 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 1862 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 1863 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 1864 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 1865 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 1866 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 1867 + //DAGB0_WR_DATA_DAGB 1868 + #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1869 + #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1870 + #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1871 + #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1872 + #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1873 + #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1874 + #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1875 + #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1876 + //DAGB0_WR_DATA_DAGB_MAX_BURST0 1877 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1878 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1879 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1880 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1881 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1882 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1883 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1884 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1885 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1886 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1887 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1888 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1889 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1890 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1891 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1892 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1893 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1894 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1895 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1896 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1897 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1898 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1899 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1900 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1901 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1902 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1903 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1904 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1905 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1906 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1907 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1908 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1909 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1910 + //DAGB0_WR_DATA_DAGB_MAX_BURST1 1911 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1912 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1913 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1914 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1915 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1916 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1917 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1918 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1919 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1920 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1921 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1922 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1923 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1924 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1925 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1926 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1927 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1928 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1929 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1930 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1931 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1932 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1933 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1934 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1935 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1936 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1937 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1938 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1939 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1940 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1941 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1942 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1943 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1944 + //DAGB0_WR_DATA_DAGB_MAX_BURST2 1945 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1946 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1947 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1948 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1949 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1950 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1951 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1952 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1953 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1954 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1955 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1956 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1957 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1958 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1959 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1960 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1961 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1962 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1963 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1964 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1965 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1966 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1967 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1968 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1969 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1970 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1971 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1972 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1973 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1974 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1975 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1976 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1977 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1978 + //DAGB0_WR_DATA_DAGB_MAX_BURST3 1979 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 1980 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 1981 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 1982 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 1983 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 1984 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 1985 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 1986 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 1987 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 1988 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 1989 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 1990 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 1991 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 1992 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 1993 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 1994 + #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 1995 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 1996 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 1997 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 1998 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 1999 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2000 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2001 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2002 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2003 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2004 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2005 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2006 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2007 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2008 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2009 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2010 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2011 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2012 + //DAGB0_WR_VC0_CNTL 2013 + #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2014 + #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2015 + #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 2016 + #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2017 + #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 2018 + #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2019 + #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 2020 + #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2021 + #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2022 + #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2023 + #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2024 + #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2025 + #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2026 + #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2027 + //DAGB0_WR_VC1_CNTL 2028 + #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2029 + #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2030 + #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 2031 + #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2032 + #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 2033 + #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2034 + #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 2035 + #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2036 + #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2037 + #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2038 + #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2039 + #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2040 + #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2041 + #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2042 + //DAGB0_WR_VC2_CNTL 2043 + #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2044 + #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2045 + #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 2046 + #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2047 + #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 2048 + #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2049 + #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 2050 + #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2051 + #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2052 + #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2053 + #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2054 + #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2055 + #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2056 + #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2057 + //DAGB0_WR_VC3_CNTL 2058 + #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2059 + #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2060 + #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 2061 + #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2062 + #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 2063 + #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2064 + #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 2065 + #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2066 + #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2067 + #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2068 + #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2069 + #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2070 + #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2071 + #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2072 + //DAGB0_WR_VC4_CNTL 2073 + #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2074 + #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2075 + #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 2076 + #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2077 + #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 2078 + #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2079 + #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 2080 + #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2081 + #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2082 + #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2083 + #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2084 + #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2085 + #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2086 + #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2087 + //DAGB0_WR_VC5_CNTL 2088 + #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2089 + #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2090 + #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 2091 + #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2092 + #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 2093 + #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2094 + #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 2095 + #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2096 + #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2097 + #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2098 + #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2099 + #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2100 + #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2101 + #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2102 + //DAGB0_WR_IO_VC_CNTL 2103 + #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2104 + #define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc 2105 + #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2106 + #define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 2107 + #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2108 + #define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 2109 + #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2110 + #define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 2111 + #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2112 + #define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 2113 + #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2114 + #define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 2115 + //DAGB0_WR_GMI_VC_CNTL 2116 + #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2117 + #define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 2118 + #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2119 + #define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 2120 + #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2121 + #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 2122 + #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2123 + #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 2124 + #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2125 + #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 2126 + #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2127 + #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 2128 + //DAGB0_WR_CNTL_MISC 2129 + #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2130 + #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 2131 + #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2132 + #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L 2133 + //DAGB0_WR_TLB_CREDIT 2134 + #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 2135 + #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 2136 + #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 2137 + #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 2138 + #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 2139 + #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 2140 + #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 2141 + #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 2142 + #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 2143 + #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 2144 + #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 2145 + #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 2146 + //DAGB0_WR_DATA_CREDIT 2147 + #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 2148 + #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 2149 + #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 2150 + #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 2151 + #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 2152 + #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 2153 + #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 2154 + #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 2155 + //DAGB0_WR_MISC_CREDIT 2156 + #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 2157 + #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 2158 + #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 2159 + #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 2160 + //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 2161 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2162 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2163 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2164 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2165 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2166 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 2167 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 2168 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 2169 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2170 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2171 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2172 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2173 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 2174 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 2175 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 2176 + #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 2177 + //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 2178 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2179 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2180 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2181 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2182 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2183 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a 2184 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b 2185 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c 2186 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2187 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2188 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2189 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2190 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L 2191 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L 2192 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L 2193 + #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L 2194 + //DAGB0_WRCLI_ASK_PENDING 2195 + #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 2196 + #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2197 + //DAGB0_WRCLI_GO_PENDING 2198 + #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 2199 + #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2200 + //DAGB0_WRCLI_GBLSEND_PENDING 2201 + #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2202 + #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2203 + //DAGB0_WRCLI_TLB_PENDING 2204 + #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 2205 + #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2206 + //DAGB0_WRCLI_OARB_PENDING 2207 + #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 2208 + #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2209 + //DAGB0_WRCLI_ASK2ARB_PENDING 2210 + #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 2211 + #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2212 + //DAGB0_WRCLI_ASK2DF_PENDING 2213 + #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 2214 + #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 2215 + //DAGB0_WRCLI_OSD_PENDING 2216 + #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 2217 + #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2218 + //DAGB0_WRCLI_ASK_OSD_PENDING 2219 + #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 2220 + #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2221 + //DAGB0_WRCLI_DBUS_ASK_PENDING 2222 + #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 2223 + #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2224 + //DAGB0_WRCLI_DBUS_GO_PENDING 2225 + #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 2226 + #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2227 + //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 2228 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 2229 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 2230 + //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 2231 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 2232 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 2233 + //DAGB0_DAGB_DLY 2234 + #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 2235 + #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 2236 + #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 2237 + #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 2238 + #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 2239 + #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 2240 + //DAGB0_CNTL_MISC 2241 + #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 2242 + #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 2243 + //DAGB0_CNTL_MISC2 2244 + #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 2245 + #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 2246 + #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 2247 + #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 2248 + #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 2249 + #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 2250 + #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 2251 + #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 2252 + #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 2253 + #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 2254 + #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 2255 + #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 2256 + #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 2257 + #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 2258 + #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 2259 + #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 2260 + #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 2261 + #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 2262 + #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 2263 + #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 2264 + #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 2265 + #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 2266 + #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 2267 + #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 2268 + //DAGB0_FIFO_EMPTY 2269 + #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 2270 + #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 2271 + //DAGB0_FIFO_FULL 2272 + #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 2273 + #define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL 2274 + //DAGB0_RD_CREDITS_FULL 2275 + #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 2276 + #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 2277 + //DAGB0_WR_CREDITS_FULL 2278 + #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 2279 + #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL 2280 + //DAGB0_PERFCOUNTER_LO 2281 + #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2282 + #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2283 + //DAGB0_PERFCOUNTER_HI 2284 + #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2285 + #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2286 + #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2287 + #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2288 + //DAGB0_PERFCOUNTER0_CFG 2289 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2290 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2291 + #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2292 + #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2293 + #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2294 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2295 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2296 + #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2297 + #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2298 + #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2299 + //DAGB0_PERFCOUNTER1_CFG 2300 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2301 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2302 + #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2303 + #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2304 + #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2305 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2306 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2307 + #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2308 + #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2309 + #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2310 + //DAGB0_PERFCOUNTER2_CFG 2311 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2312 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2313 + #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2314 + #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2315 + #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2316 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2317 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2318 + #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2319 + #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2320 + #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2321 + //DAGB0_PERFCOUNTER_RSLT_CNTL 2322 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2323 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2324 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2325 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2326 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2327 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2328 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 2329 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2330 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2331 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2332 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2333 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2334 + //DAGB0_L1TLB_REG_RW 2335 + #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 2336 + #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 2337 + #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 2338 + #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 2339 + #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 2340 + #define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 2341 + //DAGB0_RESERVE1 2342 + #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2343 + #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2344 + //DAGB0_RESERVE2 2345 + #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2346 + #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2347 + //DAGB0_RESERVE3 2348 + #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2349 + #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2350 + //DAGB0_RESERVE4 2351 + #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2352 + #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2353 + //DAGB0_SDP_RD_BW_CNTL 2354 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2355 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 2356 + #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 2357 + #define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa 2358 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd 2359 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2360 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL 2361 + #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L 2362 + #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L 2363 + #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L 2364 + //DAGB0_SDP_PRIORITY_OVERRIDE 2365 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 2366 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2367 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 2368 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 2369 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 2370 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 2371 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 2372 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 2373 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 2374 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 2375 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 2376 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 2377 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 2378 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 2379 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 2380 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 2381 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 2382 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2383 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 2384 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 2385 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 2386 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 2387 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 2388 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 2389 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 2390 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 2391 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 2392 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 2393 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 2394 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 2395 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 2396 + #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 2397 + //DAGB0_SDP_RD_PRIORITY 2398 + #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 2399 + #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 2400 + #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 2401 + #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 2402 + #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 2403 + #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 2404 + #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 2405 + #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 2406 + #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 2407 + #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 2408 + #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 2409 + #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 2410 + //DAGB0_SDP_WR_PRIORITY 2411 + #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 2412 + #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 2413 + #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 2414 + #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc 2415 + #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 2416 + #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 2417 + #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL 2418 + #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L 2419 + #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L 2420 + #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L 2421 + #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L 2422 + #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L 2423 + //DAGB0_SDP_RD_CLI2SDP_VC_MAP 2424 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2425 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2426 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2427 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2428 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2429 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2430 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2431 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2432 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2433 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2434 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2435 + #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2436 + //DAGB0_SDP_WR_CLI2SDP_VC_MAP 2437 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2438 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2439 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2440 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2441 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2442 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2443 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2444 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2445 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2446 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2447 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2448 + #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2449 + //DAGB0_SDP_ENABLE 2450 + #define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 2451 + #define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L 2452 + //DAGB0_SDP_CREDITS 2453 + #define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 2454 + #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 2455 + #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 2456 + #define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 2457 + #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 2458 + #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 2459 + //DAGB0_SDP_TAG_RESERVE0 2460 + #define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 2461 + #define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 2462 + #define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 2463 + #define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 2464 + #define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 2465 + #define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 2466 + #define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 2467 + #define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 2468 + //DAGB0_SDP_TAG_RESERVE1 2469 + #define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 2470 + #define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 2471 + #define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 2472 + #define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 2473 + #define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 2474 + #define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 2475 + #define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 2476 + #define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 2477 + //DAGB0_SDP_VCC_RESERVE0 2478 + #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 2479 + #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 2480 + #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 2481 + #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 2482 + #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 2483 + #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2484 + #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2485 + #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2486 + #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2487 + #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2488 + //DAGB0_SDP_VCC_RESERVE1 2489 + #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 2490 + #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 2491 + #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 2492 + #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2493 + #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2494 + #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2495 + #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2496 + #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2497 + //DAGB0_SDP_ERR_STATUS 2498 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 2499 + #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 2500 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 2501 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 2502 + #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 2503 + #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 2504 + #define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 2505 + #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 2506 + #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 2507 + #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 2508 + #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 2509 + #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 2510 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 2511 + #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 2512 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 2513 + #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 2514 + #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 2515 + #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 2516 + #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 2517 + #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 2518 + #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 2519 + #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 2520 + #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 2521 + #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 2522 + //DAGB0_SDP_REQ_CNTL 2523 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 2524 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 2525 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 2526 + #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 2527 + #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 2528 + #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 2529 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 2530 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 2531 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 2532 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 2533 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 2534 + #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 2535 + #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 2536 + #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 2537 + #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 2538 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 2539 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 2540 + #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 2541 + //DAGB0_SDP_MISC_AON 2542 + #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 2543 + #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 2544 + #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 2545 + #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 2546 + //DAGB0_SDP_MISC 2547 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 2548 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 2549 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 2550 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 2551 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 2552 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 2553 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 2554 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 2555 + #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 2556 + #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 2557 + #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 2558 + #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 2559 + #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 2560 + #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 2561 + #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 2562 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 2563 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 2564 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 2565 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 2566 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 2567 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 2568 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 2569 + #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 2570 + #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 2571 + #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 2572 + #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 2573 + #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 2574 + #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 2575 + #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 2576 + #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 2577 + //DAGB0_SDP_MISC2 2578 + #define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 2579 + #define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 2580 + #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 2581 + #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 2582 + #define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 2583 + #define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 2584 + #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 2585 + #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 2586 + //DAGB0_SDP_VCD_RESERVE0 2587 + #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 2588 + #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 2589 + #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 2590 + #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 2591 + #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 2592 + #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2593 + #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2594 + #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2595 + #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2596 + #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2597 + //DAGB0_SDP_VCD_RESERVE1 2598 + #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 2599 + #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 2600 + #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 2601 + #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 2602 + #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2603 + #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2604 + #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2605 + #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L 2606 + //DAGB0_SDP_ARB_CNTL0 2607 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 2608 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 2609 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 2610 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 2611 + #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 2612 + #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 2613 + #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 2614 + #define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 2615 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 2616 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 2617 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 2618 + #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 2619 + #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 2620 + #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 2621 + #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 2622 + #define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 2623 + //DAGB0_SDP_ARB_CNTL1 2624 + #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 2625 + #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 2626 + #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 2627 + #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 2628 + #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 2629 + #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 2630 + #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 2631 + #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 2632 + //DAGB0_SDP_CGTT_CLK_CTRL 2633 + #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2634 + #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2635 + #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2636 + #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2637 + #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2638 + #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2639 + #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2640 + #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2641 + #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2642 + #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2643 + //DAGB0_SDP_LATENCY_SAMPLING 2644 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 2645 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 2646 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 2647 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 2648 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 2649 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 2650 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 2651 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 2652 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 2653 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 2654 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 2655 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 2656 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 2657 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 2658 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 2659 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 2660 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 2661 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 2662 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 2663 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 2664 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 2665 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 2666 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 2667 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 2668 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 2669 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 2670 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 2671 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 2672 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 2673 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 2674 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 2675 + #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 2676 + 2677 + 2678 + // addressBlock: mmhub_pctldec 2679 + //PCTL_CTRL 2680 + #define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 2681 + #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 2682 + #define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 2683 + #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 2684 + #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 2685 + #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 2686 + #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 2687 + #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 2688 + #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 2689 + #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 2690 + #define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b 2691 + #define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c 2692 + #define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d 2693 + #define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e 2694 + #define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f 2695 + #define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 2696 + #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 2697 + #define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L 2698 + #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L 2699 + #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L 2700 + #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 2701 + #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 2702 + #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 2703 + #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 2704 + #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L 2705 + #define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L 2706 + #define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L 2707 + #define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L 2708 + #define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L 2709 + #define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L 2710 + //PCTL_MMHUB_DEEPSLEEP_IB 2711 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 2712 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 2713 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 2714 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 2715 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 2716 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 2717 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 2718 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 2719 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 2720 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 2721 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 2722 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 2723 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 2724 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 2725 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 2726 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 2727 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 2728 + #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 2729 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 2730 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 2731 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 2732 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 2733 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 2734 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 2735 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 2736 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 2737 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 2738 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 2739 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 2740 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 2741 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 2742 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 2743 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 2744 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 2745 + #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 2746 + #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 2747 + //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 2748 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 2749 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 2750 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 2751 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 2752 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 2753 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 2754 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 2755 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 2756 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 2757 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 2758 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 2759 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 2760 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 2761 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 2762 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 2763 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 2764 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 2765 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 2766 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 2767 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 2768 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 2769 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 2770 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 2771 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 2772 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 2773 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 2774 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 2775 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 2776 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 2777 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 2778 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 2779 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 2780 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 2781 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 2782 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 2783 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 2784 + //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 2785 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 2786 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 2787 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 2788 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 2789 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 2790 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 2791 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 2792 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 2793 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 2794 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 2795 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 2796 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 2797 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 2798 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 2799 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 2800 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 2801 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 2802 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 2803 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 2804 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 2805 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 2806 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 2807 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 2808 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 2809 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 2810 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 2811 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 2812 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 2813 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 2814 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 2815 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 2816 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 2817 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 2818 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 2819 + //PCTL_PG_IGNORE_DEEPSLEEP 2820 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 2821 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 2822 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 2823 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 2824 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 2825 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 2826 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 2827 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 2828 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 2829 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 2830 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 2831 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 2832 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 2833 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 2834 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 2835 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 2836 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 2837 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 2838 + #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 2839 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 2840 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 2841 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 2842 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 2843 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 2844 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 2845 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 2846 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 2847 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 2848 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 2849 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 2850 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 2851 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 2852 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 2853 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 2854 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 2855 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 2856 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 2857 + #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 2858 + //PCTL_PG_IGNORE_DEEPSLEEP_IB 2859 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 2860 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 2861 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 2862 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 2863 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 2864 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 2865 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 2866 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 2867 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 2868 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 2869 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 2870 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 2871 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 2872 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 2873 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 2874 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 2875 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 2876 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 2877 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 2878 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 2879 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 2880 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 2881 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 2882 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 2883 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 2884 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 2885 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 2886 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 2887 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 2888 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 2889 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 2890 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 2891 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 2892 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 2893 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 2894 + #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 2895 + //PCTL_SLICE0_CFG_DAGB_WRBUSY 2896 + #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 2897 + #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2898 + //PCTL_SLICE0_CFG_DAGB_RDBUSY 2899 + #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 2900 + #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2901 + //PCTL_SLICE0_CFG_DS_ALLOW 2902 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 2903 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 2904 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 2905 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 2906 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 2907 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 2908 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 2909 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 2910 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 2911 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 2912 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 2913 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 2914 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 2915 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 2916 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 2917 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 2918 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 2919 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 2920 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 2921 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 2922 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 2923 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 2924 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 2925 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 2926 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 2927 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 2928 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 2929 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 2930 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 2931 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 2932 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 2933 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 2934 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 2935 + #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 2936 + //PCTL_SLICE0_CFG_DS_ALLOW_IB 2937 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 2938 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 2939 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 2940 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 2941 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 2942 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 2943 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 2944 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 2945 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 2946 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 2947 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 2948 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 2949 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 2950 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 2951 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 2952 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 2953 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 2954 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 2955 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 2956 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 2957 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 2958 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 2959 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 2960 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 2961 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 2962 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 2963 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 2964 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 2965 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 2966 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 2967 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 2968 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 2969 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 2970 + #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 2971 + //PCTL_SLICE1_CFG_DAGB_WRBUSY 2972 + #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 2973 + #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2974 + //PCTL_SLICE1_CFG_DAGB_RDBUSY 2975 + #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 2976 + #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2977 + //PCTL_SLICE1_CFG_DS_ALLOW 2978 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 2979 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 2980 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 2981 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 2982 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 2983 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 2984 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 2985 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 2986 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 2987 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 2988 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 2989 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 2990 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 2991 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 2992 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 2993 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 2994 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 2995 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 2996 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 2997 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 2998 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 2999 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3000 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3001 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3002 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3003 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3004 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3005 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3006 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3007 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3008 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3009 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3010 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3011 + #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3012 + //PCTL_SLICE1_CFG_DS_ALLOW_IB 3013 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3014 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3015 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3016 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3017 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3018 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3019 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3020 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3021 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3022 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3023 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3024 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3025 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3026 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3027 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3028 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3029 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3030 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3031 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3032 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3033 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3034 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3035 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3036 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3037 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3038 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3039 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3040 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3041 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3042 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3043 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3044 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3045 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3046 + #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3047 + //PCTL_UTCL2_MISC 3048 + #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 3049 + #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 3050 + #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 3051 + #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 3052 + #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 3053 + #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3054 + #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3055 + #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3056 + #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3057 + #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3058 + #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL 3059 + #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 3060 + #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 3061 + #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 3062 + #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 3063 + #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3064 + #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3065 + #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3066 + #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3067 + #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3068 + //PCTL_SLICE0_MISC 3069 + #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 3070 + #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 3071 + #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 3072 + #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 3073 + #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 3074 + #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 3075 + #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3076 + #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3077 + #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3078 + #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3079 + #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3080 + #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e 3081 + #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f 3082 + #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 3083 + #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 3084 + #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 3085 + #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 3086 + #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 3087 + #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 3088 + #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3089 + #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3090 + #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3091 + #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3092 + #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3093 + #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L 3094 + #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L 3095 + //PCTL_SLICE1_MISC 3096 + #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 3097 + #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 3098 + #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 3099 + #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 3100 + #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 3101 + #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 3102 + #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3103 + #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3104 + #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3105 + #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3106 + #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3107 + #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e 3108 + #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f 3109 + #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 3110 + #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 3111 + #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 3112 + #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 3113 + #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 3114 + #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 3115 + #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3116 + #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3117 + #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3118 + #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3119 + #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3120 + #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L 3121 + #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L 3122 + //PCTL_RENG_CTRL 3123 + #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 3124 + #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3125 + #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 3126 + #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3127 + //PCTL_UTCL2_RENG_EXECUTE 3128 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3129 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3130 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3131 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 3132 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3133 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3134 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 3135 + #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 3136 + //PCTL_SLICE0_RENG_EXECUTE 3137 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3138 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3139 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3140 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 3141 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3142 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3143 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 3144 + #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 3145 + //PCTL_SLICE1_RENG_EXECUTE 3146 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3147 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3148 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3149 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 3150 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3151 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3152 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 3153 + #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 3154 + //PCTL_UTCL2_RENG_RAM_INDEX 3155 + #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3156 + #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 3157 + //PCTL_UTCL2_RENG_RAM_DATA 3158 + #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3159 + #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3160 + //PCTL_SLICE0_RENG_RAM_INDEX 3161 + #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3162 + #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 3163 + //PCTL_SLICE0_RENG_RAM_DATA 3164 + #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3165 + #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3166 + //PCTL_SLICE1_RENG_RAM_INDEX 3167 + #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3168 + #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 3169 + //PCTL_SLICE1_RENG_RAM_DATA 3170 + #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3171 + #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3172 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 3173 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3174 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3175 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3176 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3177 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 3178 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3179 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3180 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3181 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3182 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 3183 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3184 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3185 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3186 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3187 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 3188 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3189 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3190 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3191 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3192 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 3193 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3194 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3195 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3196 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3197 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 3198 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3199 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3200 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3201 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3202 + //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 3203 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3204 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3205 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3206 + #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3207 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 3208 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3209 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3210 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3211 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3212 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 3213 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3214 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3215 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3216 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3217 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 3218 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3219 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3220 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3221 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3222 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 3223 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3224 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3225 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3226 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3227 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 3228 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3229 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3230 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3231 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3232 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 3233 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3234 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3235 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3236 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3237 + //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 3238 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3239 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3240 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3241 + #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3242 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 3243 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3244 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3245 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3246 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3247 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 3248 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3249 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3250 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3251 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3252 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 3253 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3254 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3255 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3256 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3257 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 3258 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3259 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3260 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3261 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3262 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 3263 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3264 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3265 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3266 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3267 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 3268 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3269 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3270 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3271 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3272 + //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 3273 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3274 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3275 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3276 + #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3277 + //PCTL_STATUS 3278 + #define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 3279 + #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 3280 + #define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 3281 + #define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 3282 + #define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 3283 + #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 3284 + #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 3285 + #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf 3286 + #define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 3287 + #define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 3288 + #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 3289 + #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 3290 + #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 3291 + #define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L 3292 + #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L 3293 + #define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L 3294 + #define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L 3295 + #define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L 3296 + #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L 3297 + #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L 3298 + #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L 3299 + #define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L 3300 + #define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L 3301 + #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L 3302 + #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L 3303 + #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L 3304 + //PCTL_PERFCOUNTER_LO 3305 + #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3306 + #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3307 + //PCTL_PERFCOUNTER_HI 3308 + #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3309 + #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3310 + #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3311 + #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3312 + //PCTL_PERFCOUNTER0_CFG 3313 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3314 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3315 + #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3316 + #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3317 + #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3318 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3319 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3320 + #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3321 + #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3322 + #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3323 + //PCTL_PERFCOUNTER1_CFG 3324 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3325 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3326 + #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3327 + #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3328 + #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3329 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3330 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3331 + #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3332 + #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3333 + #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3334 + //PCTL_PERFCOUNTER_RSLT_CNTL 3335 + #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3336 + #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3337 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3338 + #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3339 + #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3340 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3341 + #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3342 + #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3343 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3344 + #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3345 + #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3346 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3347 + //PCTL_RESERVED_0 3348 + #define PCTL_RESERVED_0__WORD__SHIFT 0x0 3349 + #define PCTL_RESERVED_0__BYTE__SHIFT 0x10 3350 + #define PCTL_RESERVED_0__BIT7__SHIFT 0x18 3351 + #define PCTL_RESERVED_0__BIT6__SHIFT 0x19 3352 + #define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 3353 + #define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 3354 + #define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 3355 + #define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 3356 + #define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 3357 + #define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 3358 + #define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 3359 + #define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 3360 + #define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 3361 + #define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 3362 + #define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 3363 + #define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 3364 + #define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 3365 + #define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 3366 + #define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 3367 + #define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 3368 + //PCTL_RESERVED_1 3369 + #define PCTL_RESERVED_1__WORD__SHIFT 0x0 3370 + #define PCTL_RESERVED_1__BYTE__SHIFT 0x10 3371 + #define PCTL_RESERVED_1__BIT7__SHIFT 0x18 3372 + #define PCTL_RESERVED_1__BIT6__SHIFT 0x19 3373 + #define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 3374 + #define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 3375 + #define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 3376 + #define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 3377 + #define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 3378 + #define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 3379 + #define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 3380 + #define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 3381 + #define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 3382 + #define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 3383 + #define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 3384 + #define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 3385 + #define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 3386 + #define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 3387 + #define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 3388 + #define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 3389 + //PCTL_RESERVED_2 3390 + #define PCTL_RESERVED_2__WORD__SHIFT 0x0 3391 + #define PCTL_RESERVED_2__BYTE__SHIFT 0x10 3392 + #define PCTL_RESERVED_2__BIT7__SHIFT 0x18 3393 + #define PCTL_RESERVED_2__BIT6__SHIFT 0x19 3394 + #define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 3395 + #define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 3396 + #define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 3397 + #define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 3398 + #define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 3399 + #define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 3400 + #define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 3401 + #define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 3402 + #define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 3403 + #define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 3404 + #define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 3405 + #define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 3406 + #define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 3407 + #define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 3408 + #define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 3409 + #define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 3410 + //PCTL_RESERVED_3 3411 + #define PCTL_RESERVED_3__WORD__SHIFT 0x0 3412 + #define PCTL_RESERVED_3__BYTE__SHIFT 0x10 3413 + #define PCTL_RESERVED_3__BIT7__SHIFT 0x18 3414 + #define PCTL_RESERVED_3__BIT6__SHIFT 0x19 3415 + #define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 3416 + #define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 3417 + #define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 3418 + #define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 3419 + #define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 3420 + #define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 3421 + #define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 3422 + #define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 3423 + #define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 3424 + #define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 3425 + #define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 3426 + #define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 3427 + #define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 3428 + #define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 3429 + #define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 3430 + #define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 3431 + 3432 + 3433 + // addressBlock: mmhub_l1tlb_mmutcl1pfdec 3434 + //MMMC_VM_MX_L1_TLB0_STATUS 3435 + #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 3436 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3437 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3438 + #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 3439 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3440 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3441 + //MMMC_VM_MX_L1_TLB1_STATUS 3442 + #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 3443 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3444 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3445 + #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 3446 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3447 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3448 + //MMMC_VM_MX_L1_TLB2_STATUS 3449 + #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 3450 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3451 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3452 + #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 3453 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3454 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3455 + //MMMC_VM_MX_L1_TLB3_STATUS 3456 + #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 3457 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3458 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3459 + #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 3460 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3461 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3462 + //MMMC_VM_MX_L1_TLB4_STATUS 3463 + #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 3464 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3465 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3466 + #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 3467 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3468 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3469 + //MMMC_VM_MX_L1_TLB5_STATUS 3470 + #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 3471 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3472 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3473 + #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 3474 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3475 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3476 + //MMMC_VM_MX_L1_TLB6_STATUS 3477 + #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 3478 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3479 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3480 + #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 3481 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3482 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3483 + //MMMC_VM_MX_L1_TLB7_STATUS 3484 + #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 3485 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3486 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3487 + #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 3488 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3489 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3490 + 3491 + 3492 + // addressBlock: mmhub_l1tlb_mmutcl1pldec 3493 + //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 3494 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3495 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3496 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3497 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3498 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3499 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3500 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3501 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3502 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3503 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3504 + //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 3505 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3506 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3507 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3508 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3509 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3510 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3511 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3512 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3513 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3514 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3515 + //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 3516 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3517 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3518 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3519 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3520 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3521 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3522 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3523 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3524 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3525 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3526 + //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 3527 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 3528 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 3529 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 3530 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 3531 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 3532 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 3533 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 3534 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 3535 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 3536 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 3537 + //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 3538 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3539 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3540 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3541 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3542 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3543 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3544 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3545 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3546 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3547 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3548 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3549 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3550 + 3551 + 3552 + // addressBlock: mmhub_l1tlb_mmutcl1prdec 3553 + //MMMC_VM_MX_L1_PERFCOUNTER_LO 3554 + #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3555 + #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3556 + //MMMC_VM_MX_L1_PERFCOUNTER_HI 3557 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3558 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3559 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3560 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3561 + 3562 + 3563 + // addressBlock: mmhub_l1tlb_mmvmtlspfdec 3564 + //MMMC_VM_MX_L1_TLS0_CNTL 3565 + #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT 0x0 3566 + #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x4 3567 + #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x5 3568 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT 0x6 3569 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT 0x8 3570 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT 0x9 3571 + #define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT 0x10 3572 + #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK 0x0000000FL 3573 + #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000010L 3574 + #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000020L 3575 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK 0x000000C0L 3576 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK 0x00000100L 3577 + #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK 0x00000200L 3578 + #define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK 0xFFFF0000L 3579 + //MMMC_VM_MX_L1_TLS0_CNTL0 3580 + #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0 3581 + #define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT 0xc 3582 + #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd 3583 + #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x000001FFL 3584 + #define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK 0x00001000L 3585 + #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x00002000L 3586 + //MMMC_VM_MX_L1_TLS0_CNTL1 3587 + #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0 3588 + #define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT 0xc 3589 + #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd 3590 + #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x000001FFL 3591 + #define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK 0x00001000L 3592 + #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x00002000L 3593 + //MMMC_VM_MX_L1_TLS0_CNTL2 3594 + #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0 3595 + #define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT 0xc 3596 + #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd 3597 + #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x000001FFL 3598 + #define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK 0x00001000L 3599 + #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x00002000L 3600 + //MMMC_VM_MX_L1_TLS0_CNTL3 3601 + #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0 3602 + #define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT 0xc 3603 + #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd 3604 + #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x000001FFL 3605 + #define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK 0x00001000L 3606 + #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x00002000L 3607 + //MMMC_VM_MX_L1_TLS0_CNTL4 3608 + #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0 3609 + #define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT 0xc 3610 + #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd 3611 + #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x000001FFL 3612 + #define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK 0x00001000L 3613 + #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x00002000L 3614 + //MMMC_VM_MX_L1_TLS0_CNTL5 3615 + #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0 3616 + #define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT 0xc 3617 + #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd 3618 + #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x000001FFL 3619 + #define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK 0x00001000L 3620 + #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x00002000L 3621 + //MMMC_VM_MX_L1_TLS0_CNTL6 3622 + #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0 3623 + #define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT 0xc 3624 + #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd 3625 + #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x000001FFL 3626 + #define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK 0x00001000L 3627 + #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x00002000L 3628 + //MMMC_VM_MX_L1_TLS0_CNTL7 3629 + #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0 3630 + #define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT 0xc 3631 + #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd 3632 + #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x000001FFL 3633 + #define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK 0x00001000L 3634 + #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x00002000L 3635 + //MMMC_VM_MX_L1_TLS0_CNTL8 3636 + #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0 3637 + #define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT 0xc 3638 + #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd 3639 + #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x000001FFL 3640 + #define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK 0x00001000L 3641 + #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x00002000L 3642 + //MMMC_VM_MX_L1_TLS0_CNTL9 3643 + #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT 0x0 3644 + #define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT 0xc 3645 + #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT 0xd 3646 + #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK 0x000001FFL 3647 + #define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK 0x00001000L 3648 + #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK 0x00002000L 3649 + //MMMC_VM_MX_L1_TLS0_CNTL10 3650 + #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT 0x0 3651 + #define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT 0xc 3652 + #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT 0xd 3653 + #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK 0x000001FFL 3654 + #define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK 0x00001000L 3655 + #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK 0x00002000L 3656 + //MMMC_VM_MX_L1_TLS0_CNTL11 3657 + #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT 0x0 3658 + #define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT 0xc 3659 + #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT 0xd 3660 + #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK 0x000001FFL 3661 + #define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK 0x00001000L 3662 + #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK 0x00002000L 3663 + //MMMC_VM_MX_L1_TLS0_CNTL12 3664 + #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT 0x0 3665 + #define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT 0xc 3666 + #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT 0xd 3667 + #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK 0x000001FFL 3668 + #define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK 0x00001000L 3669 + #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK 0x00002000L 3670 + //MMMC_VM_MX_L1_TLS0_CNTL13 3671 + #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT 0x0 3672 + #define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT 0xc 3673 + #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT 0xd 3674 + #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK 0x000001FFL 3675 + #define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK 0x00001000L 3676 + #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK 0x00002000L 3677 + //MMMC_VM_MX_L1_TLS0_CNTL14 3678 + #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT 0x0 3679 + #define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT 0xc 3680 + #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT 0xd 3681 + #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK 0x000001FFL 3682 + #define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK 0x00001000L 3683 + #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK 0x00002000L 3684 + //MMMC_VM_MX_L1_TLS0_CNTL15 3685 + #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT 0x0 3686 + #define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT 0xc 3687 + #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT 0xd 3688 + #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK 0x000001FFL 3689 + #define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK 0x00001000L 3690 + #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK 0x00002000L 3691 + //MMMC_VM_MX_L1_TLS0_CNTL16 3692 + #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT 0x0 3693 + #define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT 0xc 3694 + #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT 0xd 3695 + #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK 0x000001FFL 3696 + #define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK 0x00001000L 3697 + #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK 0x00002000L 3698 + //MMMC_VM_MX_L1_TLS0_CNTL17 3699 + #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT 0x0 3700 + #define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT 0xc 3701 + #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT 0xd 3702 + #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK 0x000001FFL 3703 + #define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK 0x00001000L 3704 + #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK 0x00002000L 3705 + //MMMC_VM_MX_L1_TLS0_CNTL18 3706 + #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT 0x0 3707 + #define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT 0xc 3708 + #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT 0xd 3709 + #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK 0x000001FFL 3710 + #define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK 0x00001000L 3711 + #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK 0x00002000L 3712 + //MMMC_VM_MX_L1_TLS0_CNTL19 3713 + #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT 0x0 3714 + #define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT 0xc 3715 + #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT 0xd 3716 + #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK 0x000001FFL 3717 + #define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK 0x00001000L 3718 + #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK 0x00002000L 3719 + //MMMC_VM_MX_L1_TLS0_CNTL20 3720 + #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT 0x0 3721 + #define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT 0xc 3722 + #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT 0xd 3723 + #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK 0x000001FFL 3724 + #define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK 0x00001000L 3725 + #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK 0x00002000L 3726 + //MMMC_VM_MX_L1_TLS0_CNTL21 3727 + #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT 0x0 3728 + #define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT 0xc 3729 + #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT 0xd 3730 + #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK 0x000001FFL 3731 + #define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK 0x00001000L 3732 + #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK 0x00002000L 3733 + //MMMC_VM_MX_L1_TLS0_CNTL22 3734 + #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT 0x0 3735 + #define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT 0xc 3736 + #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT 0xd 3737 + #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK 0x000001FFL 3738 + #define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK 0x00001000L 3739 + #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK 0x00002000L 3740 + //MMMC_VM_MX_L1_TLS0_CNTL23 3741 + #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT 0x0 3742 + #define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT 0xc 3743 + #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT 0xd 3744 + #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK 0x000001FFL 3745 + #define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK 0x00001000L 3746 + #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK 0x00002000L 3747 + //MMMC_VM_MX_L1_TLS0_CNTL24 3748 + #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT 0x0 3749 + #define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT 0xc 3750 + #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT 0xd 3751 + #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK 0x000001FFL 3752 + #define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK 0x00001000L 3753 + #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK 0x00002000L 3754 + //MMMC_VM_MX_L1_TLS0_CNTL25 3755 + #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT 0x0 3756 + #define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT 0xc 3757 + #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT 0xd 3758 + #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK 0x000001FFL 3759 + #define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK 0x00001000L 3760 + #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK 0x00002000L 3761 + //MMMC_VM_MX_L1_TLS0_CNTL26 3762 + #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT 0x0 3763 + #define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT 0xc 3764 + #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT 0xd 3765 + #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK 0x000001FFL 3766 + #define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK 0x00001000L 3767 + #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK 0x00002000L 3768 + //MMMC_VM_MX_L1_TLS0_CNTL27 3769 + #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT 0x0 3770 + #define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT 0xc 3771 + #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT 0xd 3772 + #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK 0x000001FFL 3773 + #define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK 0x00001000L 3774 + #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK 0x00002000L 3775 + //MMMC_VM_MX_L1_TLS0_CNTL28 3776 + #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT 0x0 3777 + #define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT 0xc 3778 + #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT 0xd 3779 + #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK 0x000001FFL 3780 + #define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK 0x00001000L 3781 + #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK 0x00002000L 3782 + //MMMC_VM_MX_L1_TLS0_CNTL29 3783 + #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT 0x0 3784 + #define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT 0xc 3785 + #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT 0xd 3786 + #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK 0x000001FFL 3787 + #define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK 0x00001000L 3788 + #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK 0x00002000L 3789 + //MMMC_VM_MX_L1_TLS0_CNTL30 3790 + #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT 0x0 3791 + #define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT 0xc 3792 + #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT 0xd 3793 + #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK 0x000001FFL 3794 + #define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK 0x00001000L 3795 + #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK 0x00002000L 3796 + //MMMC_VM_MX_L1_TLS0_CNTL31 3797 + #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT 0x0 3798 + #define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT 0xc 3799 + #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT 0xd 3800 + #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK 0x000001FFL 3801 + #define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK 0x00001000L 3802 + #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK 0x00002000L 3803 + //MMMC_VM_MX_L1_TLS0_CNTL32 3804 + #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT 0x0 3805 + #define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT 0xc 3806 + #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT 0xd 3807 + #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK 0x000001FFL 3808 + #define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK 0x00001000L 3809 + #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK 0x00002000L 3810 + //MMMC_VM_MX_L1_TLS0_CNTL33 3811 + #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT 0x0 3812 + #define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT 0xc 3813 + #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT 0xd 3814 + #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK 0x000001FFL 3815 + #define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK 0x00001000L 3816 + #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK 0x00002000L 3817 + //MMMC_VM_MX_L1_TLS0_CNTL34 3818 + #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT 0x0 3819 + #define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT 0xc 3820 + #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT 0xd 3821 + #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK 0x000001FFL 3822 + #define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK 0x00001000L 3823 + #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK 0x00002000L 3824 + //MMMC_VM_MX_L1_TLS0_CNTL35 3825 + #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT 0x0 3826 + #define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT 0xc 3827 + #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT 0xd 3828 + #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK 0x000001FFL 3829 + #define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK 0x00001000L 3830 + #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK 0x00002000L 3831 + //MMMC_VM_MX_L1_TLS0_CNTL36 3832 + #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT 0x0 3833 + #define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT 0xc 3834 + #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT 0xd 3835 + #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK 0x000001FFL 3836 + #define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK 0x00001000L 3837 + #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK 0x00002000L 3838 + //MMMC_VM_MX_L1_TLS0_CNTL37 3839 + #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT 0x0 3840 + #define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT 0xc 3841 + #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT 0xd 3842 + #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK 0x000001FFL 3843 + #define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK 0x00001000L 3844 + #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK 0x00002000L 3845 + //MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 3846 + #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT 0x0 3847 + #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3848 + //MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 3849 + #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT 0x0 3850 + #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK 0x0000000FL 3851 + //MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 3852 + #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT 0x0 3853 + #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3854 + //MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 3855 + #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT 0x0 3856 + #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK 0x0000000FL 3857 + //MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 3858 + #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT 0x0 3859 + #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3860 + //MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 3861 + #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT 0x0 3862 + #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK 0x0000000FL 3863 + //MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 3864 + #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT 0x0 3865 + #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3866 + //MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 3867 + #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT 0x0 3868 + #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK 0x0000000FL 3869 + //MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 3870 + #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT 0x0 3871 + #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3872 + //MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 3873 + #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT 0x0 3874 + #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK 0x0000000FL 3875 + //MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 3876 + #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT 0x0 3877 + #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3878 + //MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 3879 + #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT 0x0 3880 + #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK 0x0000000FL 3881 + //MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 3882 + #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT 0x0 3883 + #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3884 + //MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 3885 + #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT 0x0 3886 + #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK 0x0000000FL 3887 + //MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 3888 + #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT 0x0 3889 + #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3890 + //MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 3891 + #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT 0x0 3892 + #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK 0x0000000FL 3893 + //MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 3894 + #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT 0x0 3895 + #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3896 + //MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 3897 + #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT 0x0 3898 + #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK 0x0000000FL 3899 + //MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 3900 + #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT 0x0 3901 + #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3902 + //MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 3903 + #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT 0x0 3904 + #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK 0x0000000FL 3905 + //MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 3906 + #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT 0x0 3907 + #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3908 + //MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 3909 + #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT 0x0 3910 + #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK 0x0000000FL 3911 + //MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 3912 + #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT 0x0 3913 + #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3914 + //MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 3915 + #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT 0x0 3916 + #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK 0x0000000FL 3917 + //MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 3918 + #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT 0x0 3919 + #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3920 + //MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 3921 + #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT 0x0 3922 + #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK 0x0000000FL 3923 + //MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 3924 + #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT 0x0 3925 + #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3926 + //MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 3927 + #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT 0x0 3928 + #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK 0x0000000FL 3929 + //MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 3930 + #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT 0x0 3931 + #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3932 + //MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 3933 + #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT 0x0 3934 + #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK 0x0000000FL 3935 + //MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 3936 + #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT 0x0 3937 + #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3938 + //MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 3939 + #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT 0x0 3940 + #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK 0x0000000FL 3941 + //MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 3942 + #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT 0x0 3943 + #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3944 + //MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 3945 + #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT 0x0 3946 + #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK 0x0000000FL 3947 + //MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 3948 + #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT 0x0 3949 + #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3950 + //MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 3951 + #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT 0x0 3952 + #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK 0x0000000FL 3953 + //MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 3954 + #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT 0x0 3955 + #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3956 + //MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 3957 + #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT 0x0 3958 + #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK 0x0000000FL 3959 + //MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 3960 + #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT 0x0 3961 + #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3962 + //MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 3963 + #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT 0x0 3964 + #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK 0x0000000FL 3965 + //MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 3966 + #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT 0x0 3967 + #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3968 + //MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 3969 + #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT 0x0 3970 + #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK 0x0000000FL 3971 + //MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 3972 + #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT 0x0 3973 + #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3974 + //MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 3975 + #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT 0x0 3976 + #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK 0x0000000FL 3977 + //MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 3978 + #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT 0x0 3979 + #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3980 + //MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 3981 + #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT 0x0 3982 + #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK 0x0000000FL 3983 + //MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 3984 + #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT 0x0 3985 + #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3986 + //MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 3987 + #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT 0x0 3988 + #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK 0x0000000FL 3989 + //MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 3990 + #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT 0x0 3991 + #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3992 + //MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 3993 + #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT 0x0 3994 + #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK 0x0000000FL 3995 + //MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 3996 + #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT 0x0 3997 + #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 3998 + //MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 3999 + #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT 0x0 4000 + #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK 0x0000000FL 4001 + //MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 4002 + #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT 0x0 4003 + #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4004 + //MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 4005 + #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT 0x0 4006 + #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK 0x0000000FL 4007 + //MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 4008 + #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT 0x0 4009 + #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4010 + //MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 4011 + #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT 0x0 4012 + #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK 0x0000000FL 4013 + //MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 4014 + #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT 0x0 4015 + #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4016 + //MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 4017 + #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT 0x0 4018 + #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK 0x0000000FL 4019 + //MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 4020 + #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT 0x0 4021 + #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4022 + //MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 4023 + #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT 0x0 4024 + #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK 0x0000000FL 4025 + //MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 4026 + #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT 0x0 4027 + #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4028 + //MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 4029 + #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT 0x0 4030 + #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK 0x0000000FL 4031 + //MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 4032 + #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT 0x0 4033 + #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4034 + //MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 4035 + #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT 0x0 4036 + #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK 0x0000000FL 4037 + //MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 4038 + #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT 0x0 4039 + #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4040 + //MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 4041 + #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT 0x0 4042 + #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK 0x0000000FL 4043 + //MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 4044 + #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT 0x0 4045 + #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4046 + //MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 4047 + #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT 0x0 4048 + #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK 0x0000000FL 4049 + //MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 4050 + #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT 0x0 4051 + #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4052 + //MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 4053 + #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT 0x0 4054 + #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK 0x0000000FL 4055 + //MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 4056 + #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT 0x0 4057 + #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4058 + //MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 4059 + #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT 0x0 4060 + #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK 0x0000000FL 4061 + //MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 4062 + #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT 0x0 4063 + #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4064 + //MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 4065 + #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT 0x0 4066 + #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK 0x0000000FL 4067 + //MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 4068 + #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT 0x0 4069 + #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 4070 + //MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 4071 + #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT 0x0 4072 + #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK 0x0000000FL 4073 + //MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 4074 + #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT 0x0 4075 + #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4076 + //MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 4077 + #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT 0x0 4078 + #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK 0x0000000FL 4079 + //MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 4080 + #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT 0x0 4081 + #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4082 + //MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 4083 + #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT 0x0 4084 + #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK 0x0000000FL 4085 + //MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 4086 + #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT 0x0 4087 + #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4088 + //MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 4089 + #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT 0x0 4090 + #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK 0x0000000FL 4091 + //MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 4092 + #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT 0x0 4093 + #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4094 + //MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 4095 + #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT 0x0 4096 + #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK 0x0000000FL 4097 + //MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 4098 + #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT 0x0 4099 + #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4100 + //MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 4101 + #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT 0x0 4102 + #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK 0x0000000FL 4103 + //MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 4104 + #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT 0x0 4105 + #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4106 + //MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 4107 + #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT 0x0 4108 + #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK 0x0000000FL 4109 + //MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 4110 + #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT 0x0 4111 + #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4112 + //MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 4113 + #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT 0x0 4114 + #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK 0x0000000FL 4115 + //MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 4116 + #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT 0x0 4117 + #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4118 + //MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 4119 + #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT 0x0 4120 + #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK 0x0000000FL 4121 + //MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 4122 + #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT 0x0 4123 + #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4124 + //MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 4125 + #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT 0x0 4126 + #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK 0x0000000FL 4127 + //MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 4128 + #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT 0x0 4129 + #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4130 + //MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 4131 + #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT 0x0 4132 + #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK 0x0000000FL 4133 + //MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 4134 + #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT 0x0 4135 + #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4136 + //MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 4137 + #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT 0x0 4138 + #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK 0x0000000FL 4139 + //MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 4140 + #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT 0x0 4141 + #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4142 + //MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 4143 + #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT 0x0 4144 + #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK 0x0000000FL 4145 + //MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 4146 + #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT 0x0 4147 + #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4148 + //MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 4149 + #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT 0x0 4150 + #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK 0x0000000FL 4151 + //MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 4152 + #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT 0x0 4153 + #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4154 + //MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 4155 + #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT 0x0 4156 + #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK 0x0000000FL 4157 + //MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 4158 + #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT 0x0 4159 + #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4160 + //MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 4161 + #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT 0x0 4162 + #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK 0x0000000FL 4163 + //MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 4164 + #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT 0x0 4165 + #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4166 + //MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 4167 + #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT 0x0 4168 + #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK 0x0000000FL 4169 + //MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 4170 + #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT 0x0 4171 + #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4172 + //MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 4173 + #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT 0x0 4174 + #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK 0x0000000FL 4175 + //MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 4176 + #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT 0x0 4177 + #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4178 + //MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 4179 + #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT 0x0 4180 + #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK 0x0000000FL 4181 + //MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 4182 + #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT 0x0 4183 + #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4184 + //MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 4185 + #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT 0x0 4186 + #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK 0x0000000FL 4187 + //MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 4188 + #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT 0x0 4189 + #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4190 + //MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 4191 + #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT 0x0 4192 + #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK 0x0000000FL 4193 + //MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 4194 + #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT 0x0 4195 + #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4196 + //MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 4197 + #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT 0x0 4198 + #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK 0x0000000FL 4199 + //MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 4200 + #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT 0x0 4201 + #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4202 + //MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 4203 + #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT 0x0 4204 + #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK 0x0000000FL 4205 + //MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 4206 + #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT 0x0 4207 + #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4208 + //MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 4209 + #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT 0x0 4210 + #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK 0x0000000FL 4211 + //MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 4212 + #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT 0x0 4213 + #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4214 + //MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 4215 + #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT 0x0 4216 + #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK 0x0000000FL 4217 + //MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 4218 + #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT 0x0 4219 + #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4220 + //MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 4221 + #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT 0x0 4222 + #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK 0x0000000FL 4223 + //MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 4224 + #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT 0x0 4225 + #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4226 + //MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 4227 + #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT 0x0 4228 + #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK 0x0000000FL 4229 + //MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 4230 + #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT 0x0 4231 + #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4232 + //MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 4233 + #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT 0x0 4234 + #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK 0x0000000FL 4235 + //MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 4236 + #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT 0x0 4237 + #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4238 + //MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 4239 + #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT 0x0 4240 + #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK 0x0000000FL 4241 + //MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 4242 + #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT 0x0 4243 + #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4244 + //MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 4245 + #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT 0x0 4246 + #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK 0x0000000FL 4247 + //MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 4248 + #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT 0x0 4249 + #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4250 + //MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 4251 + #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT 0x0 4252 + #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK 0x0000000FL 4253 + //MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 4254 + #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT 0x0 4255 + #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4256 + //MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 4257 + #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT 0x0 4258 + #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK 0x0000000FL 4259 + //MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 4260 + #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT 0x0 4261 + #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4262 + //MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 4263 + #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT 0x0 4264 + #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK 0x0000000FL 4265 + //MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 4266 + #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT 0x0 4267 + #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4268 + //MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 4269 + #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT 0x0 4270 + #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK 0x0000000FL 4271 + //MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 4272 + #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT 0x0 4273 + #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4274 + //MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 4275 + #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT 0x0 4276 + #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK 0x0000000FL 4277 + //MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 4278 + #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT 0x0 4279 + #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4280 + //MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 4281 + #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT 0x0 4282 + #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK 0x0000000FL 4283 + //MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 4284 + #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT 0x0 4285 + #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4286 + //MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 4287 + #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT 0x0 4288 + #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK 0x0000000FL 4289 + //MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 4290 + #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT 0x0 4291 + #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4292 + //MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 4293 + #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT 0x0 4294 + #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK 0x0000000FL 4295 + //MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 4296 + #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT 0x0 4297 + #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 4298 + //MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 4299 + #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT 0x0 4300 + #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK 0x0000000FL 4301 + //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 4302 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT 0x0 4303 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK 0xFFFFFFFFL 4304 + //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 4305 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT 0x0 4306 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK 0x0000003FL 4307 + //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 4308 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT 0x0 4309 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK 0xFFFFFFFFL 4310 + //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 4311 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT 0x0 4312 + #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK 0x0000003FL 4313 + //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 4314 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 4315 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc 4316 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 4317 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 4318 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 4319 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000FFL 4320 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x001FF000L 4321 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L 4322 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1E000000L 4323 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000L 4324 + //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 4325 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4326 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4327 + //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 4328 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4329 + #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4330 + //MMVM_L2_SAW_CNTL 4331 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4332 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4333 + #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4334 + #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4335 + #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4336 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4337 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4338 + #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4339 + #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4340 + #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4341 + #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4342 + #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4343 + #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4344 + #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 4345 + #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 4346 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4347 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4348 + #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4349 + #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4350 + #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4351 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4352 + #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4353 + #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4354 + #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4355 + #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4356 + #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4357 + #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4358 + #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4359 + #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L 4360 + #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 4361 + //MMVM_L2_SAW_CNTL2 4362 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4363 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4364 + #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4365 + #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4366 + #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 4367 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4368 + #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4369 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4370 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4371 + #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4372 + #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4373 + #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 4374 + #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4375 + #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4376 + //MMVM_L2_SAW_CNTL3 4377 + #define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 4378 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4379 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4380 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4381 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4382 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4383 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4384 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4385 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4386 + #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4387 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4388 + #define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL 4389 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4390 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4391 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4392 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4393 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4394 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4395 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4396 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4397 + #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4398 + #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4399 + //MMVM_L2_SAW_CNTL4 4400 + #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4401 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4402 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 4403 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 4404 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 4405 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 4406 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 4407 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 4408 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 4409 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 4410 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 4411 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 4412 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 4413 + #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 4414 + #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4415 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4416 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L 4417 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L 4418 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L 4419 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L 4420 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L 4421 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L 4422 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L 4423 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L 4424 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L 4425 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L 4426 + #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L 4427 + #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L 4428 + //MMVM_L2_SAW_CONTEXT0_CNTL 4429 + #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4430 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4431 + #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 4432 + #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4433 + #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 4434 + #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4435 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4436 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4437 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 4438 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 4439 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 4440 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 4441 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4442 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4443 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 4444 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 4445 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 4446 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 4447 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4448 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4449 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 4450 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 4451 + #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x1c 4452 + #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x1d 4453 + #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4454 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4455 + #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 4456 + #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4457 + #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 4458 + #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4459 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4460 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4461 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 4462 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 4463 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 4464 + #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 4465 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4466 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4467 + #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 4468 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 4469 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 4470 + #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 4471 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4472 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4473 + #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 4474 + #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L 4475 + #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L 4476 + #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L 4477 + //MMVM_L2_SAW_CONTEXT0_CNTL2 4478 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4479 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 4480 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 4481 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 4482 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 4483 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4484 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 4485 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 4486 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 4487 + #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 4488 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 4489 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4490 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4491 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 4492 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4493 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4494 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 4495 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4496 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4497 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 4498 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4499 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4500 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 4501 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4502 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4503 + //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 4504 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4505 + #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4506 + //MMVM_L2_SAW_CONTEXTS_DISABLE 4507 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 4508 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 4509 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 4510 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 4511 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 4512 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 4513 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 4514 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 4515 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 4516 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 4517 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 4518 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 4519 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 4520 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 4521 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 4522 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 4523 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 4524 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 4525 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 4526 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 4527 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 4528 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 4529 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 4530 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 4531 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 4532 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 4533 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 4534 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 4535 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 4536 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 4537 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 4538 + #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 4539 + //MMVM_L2_SAW_PIPES_BUSY_LO32 4540 + #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT 0x0 4541 + #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL 4542 + //MMVM_L2_SAW_PIPES_BUSY_HI32 4543 + #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT 0x0 4544 + #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL 4545 + //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 4546 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 4547 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT 0x1 4548 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT 0x3 4549 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 4550 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK 0x00000006L 4551 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK 0x000001F8L 4552 + //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 4553 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4554 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4555 + //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 4556 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4557 + #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4558 + 4559 + 4560 + // addressBlock: mmhub_mmutcl2_mmatcl2dec 4561 + //MM_ATC_L2_CNTL 4562 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 4563 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 4564 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 4565 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 4566 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 4567 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 4568 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 4569 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 4570 + #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 4571 + #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 4572 + #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 4573 + #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 4574 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 4575 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 4576 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 4577 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 4578 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 4579 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 4580 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 4581 + #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 4582 + #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 4583 + #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 4584 + #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L 4585 + #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L 4586 + //MM_ATC_L2_CNTL2 4587 + #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 4588 + #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 4589 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 4590 + #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb 4591 + #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc 4592 + #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf 4593 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 4594 + #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 4595 + #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L 4596 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L 4597 + #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L 4598 + #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L 4599 + #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L 4600 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L 4601 + //MM_ATC_L2_CACHE_DATA0 4602 + #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 4603 + #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 4604 + #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 4605 + #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 4606 + #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 4607 + #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 4608 + #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 4609 + #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 4610 + //MM_ATC_L2_CACHE_DATA1 4611 + #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 4612 + #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 4613 + //MM_ATC_L2_CACHE_DATA2 4614 + #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 4615 + #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 4616 + //MM_ATC_L2_CNTL3 4617 + #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 4618 + #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 4619 + #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 4620 + #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 4621 + #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 4622 + #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b 4623 + #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e 4624 + #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 4625 + #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 4626 + #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 4627 + #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L 4628 + #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L 4629 + #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L 4630 + #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L 4631 + //MM_ATC_L2_CNTL4 4632 + #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 4633 + #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 4634 + #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 4635 + #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 4636 + #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 4637 + #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 4638 + //MM_ATC_L2_CNTL5 4639 + #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 4640 + #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 4641 + #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 4642 + #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 4643 + //MM_ATC_L2_MM_GROUP_RT_CLASSES 4644 + #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 4645 + #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 4646 + //MM_ATC_L2_STATUS 4647 + #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 4648 + #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 4649 + #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 4650 + #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L 4651 + //MM_ATC_L2_STATUS2 4652 + #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 4653 + #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 4654 + #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 4655 + #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 4656 + //MM_ATC_L2_MISC_CG 4657 + #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 4658 + #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 4659 + #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 4660 + #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 4661 + #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 4662 + #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 4663 + //MM_ATC_L2_MEM_POWER_LS 4664 + #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 4665 + #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 4666 + #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 4667 + #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 4668 + //MM_ATC_L2_CGTT_CLK_CTRL 4669 + #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4670 + #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4671 + #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4672 + #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4673 + #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4674 + #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4675 + #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4676 + #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 4677 + #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4678 + #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4679 + //MM_ATC_L2_SDPPORT_CTRL 4680 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 4681 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 4682 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 4683 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 4684 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 4685 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 4686 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 4687 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 4688 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 4689 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 4690 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 4691 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 4692 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 4693 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 4694 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 4695 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 4696 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 4697 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 4698 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 4699 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 4700 + 4701 + 4702 + // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4703 + //MMVM_L2_CNTL 4704 + #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4705 + #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4706 + #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4707 + #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4708 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4709 + #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4710 + #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4711 + #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4712 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4713 + #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4714 + #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4715 + #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4716 + #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4717 + #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4718 + #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4719 + #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4720 + #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4721 + #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4722 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4723 + #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4724 + #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4725 + #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4726 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4727 + #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4728 + #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4729 + #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4730 + #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4731 + #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4732 + //MMVM_L2_CNTL2 4733 + #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4734 + #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4735 + #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4736 + #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4737 + #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4738 + #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4739 + #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4740 + #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4741 + #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4742 + #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4743 + #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4744 + #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4745 + #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4746 + #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4747 + //MMVM_L2_CNTL3 4748 + #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4749 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4750 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4751 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4752 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4753 + #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4754 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4755 + #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4756 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4757 + #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4758 + #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4759 + #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4760 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4761 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4762 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4763 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4764 + #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4765 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4766 + #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4767 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4768 + #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4769 + #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4770 + //MMVM_L2_STATUS 4771 + #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4772 + #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4773 + #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4774 + #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4775 + #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4776 + #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 4777 + #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 4778 + #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 4779 + #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 4780 + #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 4781 + #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 4782 + #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 4783 + #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 4784 + #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 4785 + //MMVM_DUMMY_PAGE_FAULT_CNTL 4786 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 4787 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 4788 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 4789 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 4790 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 4791 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 4792 + //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 4793 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 4794 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4795 + //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 4796 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 4797 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 4798 + //MMVM_INVALIDATE_CNTL 4799 + #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 4800 + #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 4801 + #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 4802 + #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 4803 + //MMVM_L2_PROTECTION_FAULT_CNTL 4804 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4805 + #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 4806 + #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 4807 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 4808 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4809 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 4810 + #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 4811 + #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4812 + #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 4813 + #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 4814 + #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4815 + #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 4816 + #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4817 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 4818 + #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 4819 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 4820 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 4821 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4822 + #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 4823 + #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 4824 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 4825 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4826 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 4827 + #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 4828 + #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4829 + #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 4830 + #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 4831 + #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4832 + #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 4833 + #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4834 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 4835 + #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 4836 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 4837 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 4838 + //MMVM_L2_PROTECTION_FAULT_CNTL2 4839 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 4840 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 4841 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 4842 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 4843 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 4844 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 4845 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 4846 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 4847 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 4848 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 4849 + //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 4850 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4851 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4852 + //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 4853 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4854 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4855 + //MMVM_L2_PROTECTION_FAULT_STATUS 4856 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 4857 + #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 4858 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 4859 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 4860 + #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 4861 + #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 4862 + #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 4863 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 4864 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 4865 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 4866 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d 4867 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 4868 + #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 4869 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 4870 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 4871 + #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 4872 + #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 4873 + #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 4874 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 4875 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 4876 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 4877 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L 4878 + //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 4879 + #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4880 + #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4881 + //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 4882 + #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4883 + #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4884 + //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 4885 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 4886 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4887 + //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 4888 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 4889 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4890 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 4891 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4892 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4893 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 4894 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4895 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4896 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 4897 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4898 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4899 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 4900 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4901 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4902 + //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 4903 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 4904 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 4905 + //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 4906 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 4907 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 4908 + //MMVM_L2_CNTL4 4909 + #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4910 + #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4911 + #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 4912 + #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 4913 + #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 4914 + #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 4915 + #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 4916 + #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 4917 + #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f 4918 + #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4919 + #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4920 + #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 4921 + #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 4922 + #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 4923 + #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 4924 + #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 4925 + #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 4926 + #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L 4927 + //MMVM_L2_MM_GROUP_RT_CLASSES 4928 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 4929 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 4930 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 4931 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 4932 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 4933 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 4934 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 4935 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 4936 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 4937 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 4938 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 4939 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 4940 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 4941 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 4942 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 4943 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 4944 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 4945 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 4946 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 4947 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 4948 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 4949 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 4950 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 4951 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 4952 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 4953 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 4954 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 4955 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 4956 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 4957 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 4958 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 4959 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 4960 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 4961 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 4962 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 4963 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 4964 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 4965 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 4966 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 4967 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 4968 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 4969 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 4970 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 4971 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 4972 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 4973 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 4974 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 4975 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 4976 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 4977 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 4978 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 4979 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 4980 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 4981 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 4982 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 4983 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 4984 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 4985 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 4986 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 4987 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 4988 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 4989 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 4990 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 4991 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 4992 + //MMVM_L2_BANK_SELECT_RESERVED_CID 4993 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4994 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4995 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 4996 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4997 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4998 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4999 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5000 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5001 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 5002 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5003 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5004 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5005 + //MMVM_L2_BANK_SELECT_RESERVED_CID2 5006 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5007 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5008 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 5009 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5010 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5011 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5012 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5013 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5014 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 5015 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5016 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5017 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5018 + //MMVM_L2_CACHE_PARITY_CNTL 5019 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 5020 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 5021 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 5022 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 5023 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 5024 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 5025 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 5026 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 5027 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 5028 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 5029 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 5030 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 5031 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 5032 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 5033 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 5034 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 5035 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 5036 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 5037 + //MMVM_L2_CGTT_CLK_CTRL 5038 + #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5039 + #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 5040 + #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 5041 + #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 5042 + #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 5043 + #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 5044 + #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 5045 + #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 5046 + #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 5047 + #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 5048 + //MMVM_L2_CNTL5 5049 + #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 5050 + #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 5051 + #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe 5052 + #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf 5053 + #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 5054 + #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 5055 + #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 5056 + #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 5057 + #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L 5058 + #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L 5059 + #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L 5060 + #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L 5061 + //MMVM_L2_GCR_CNTL 5062 + #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 5063 + #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 5064 + #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 5065 + #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 5066 + //MMVM_L2_CGTT_BUSY_CTRL 5067 + #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 5068 + #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 5069 + #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 5070 + #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 5071 + //MMVM_L2_PTE_CACHE_DUMP_CNTL 5072 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 5073 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 5074 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 5075 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 5076 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 5077 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 5078 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 5079 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 5080 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 5081 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 5082 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 5083 + #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 5084 + //MMVM_L2_PTE_CACHE_DUMP_READ 5085 + #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 5086 + #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 5087 + //MMVM_L2_BANK_SELECT_MASKS 5088 + #define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 5089 + #define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 5090 + #define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 5091 + #define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc 5092 + #define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL 5093 + #define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L 5094 + #define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L 5095 + #define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L 5096 + //MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 5097 + #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 5098 + #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa 5099 + #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL 5100 + #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L 5101 + //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 5102 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 5103 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa 5104 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL 5105 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L 5106 + //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 5107 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 5108 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa 5109 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL 5110 + #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L 5111 + //MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 5112 + #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 5113 + #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa 5114 + #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL 5115 + #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L 5116 + //MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 5117 + #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 5118 + #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa 5119 + #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 5120 + #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L 5121 + 5122 + 5123 + // addressBlock: mmhub_mmutcl2_mmvml2vcdec 5124 + //MMVM_CONTEXT0_CNTL 5125 + #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5126 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5127 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5128 + #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5129 + #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5130 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5131 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5132 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5133 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5134 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5135 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5136 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5137 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5138 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5139 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5140 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5141 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5142 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5143 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5144 + #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5145 + #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5146 + #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5147 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5148 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5149 + #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5150 + #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5151 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5152 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5153 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5154 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5155 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5156 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5157 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5158 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5159 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5160 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5161 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5162 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5163 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5164 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5165 + #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5166 + #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5167 + //MMVM_CONTEXT1_CNTL 5168 + #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5169 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5170 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5171 + #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5172 + #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5173 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5174 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5175 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5176 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5177 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5178 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5179 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5180 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5181 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5182 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5183 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5184 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5185 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5186 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5187 + #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5188 + #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5189 + #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5190 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5191 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5192 + #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5193 + #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5194 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5195 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5196 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5197 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5198 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5199 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5200 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5201 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5202 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5203 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5204 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5205 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5206 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5207 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5208 + #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5209 + #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5210 + //MMVM_CONTEXT2_CNTL 5211 + #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5212 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5213 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5214 + #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5215 + #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5216 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5217 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5218 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5219 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5220 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5221 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5222 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5223 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5224 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5225 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5226 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5227 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5228 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5229 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5230 + #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5231 + #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5232 + #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5233 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5234 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5235 + #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5236 + #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5237 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5238 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5239 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5240 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5241 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5242 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5243 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5244 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5245 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5246 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5247 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5248 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5249 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5250 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5251 + #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5252 + #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5253 + //MMVM_CONTEXT3_CNTL 5254 + #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5255 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5256 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5257 + #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5258 + #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5259 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5260 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5261 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5262 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5263 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5264 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5265 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5266 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5267 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5268 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5269 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5270 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5271 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5272 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5273 + #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5274 + #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5275 + #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5276 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5277 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5278 + #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5279 + #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5280 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5281 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5282 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5283 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5284 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5285 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5286 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5287 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5288 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5289 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5290 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5291 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5292 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5293 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5294 + #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5295 + #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5296 + //MMVM_CONTEXT4_CNTL 5297 + #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5298 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5299 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5300 + #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5301 + #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5302 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5303 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5304 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5305 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5306 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5307 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5308 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5309 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5310 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5311 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5312 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5313 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5314 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5315 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5316 + #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5317 + #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5318 + #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5319 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5320 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5321 + #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5322 + #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5323 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5324 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5325 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5326 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5327 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5328 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5329 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5330 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5331 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5332 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5333 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5334 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5335 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5336 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5337 + #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5338 + #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5339 + //MMVM_CONTEXT5_CNTL 5340 + #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5341 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5342 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5343 + #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5344 + #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5345 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5346 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5347 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5348 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5349 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5350 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5351 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5352 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5353 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5354 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5355 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5356 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5357 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5358 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5359 + #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5360 + #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5361 + #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5362 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5363 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5364 + #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5365 + #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5366 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5367 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5368 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5369 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5370 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5371 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5372 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5373 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5374 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5375 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5376 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5377 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5378 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5379 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5380 + #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5381 + #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5382 + //MMVM_CONTEXT6_CNTL 5383 + #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5384 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5385 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5386 + #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5387 + #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5388 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5389 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5390 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5391 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5392 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5393 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5394 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5395 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5396 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5397 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5398 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5399 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5400 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5401 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5402 + #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5403 + #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5404 + #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5405 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5406 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5407 + #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5408 + #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5409 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5410 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5411 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5412 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5413 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5414 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5415 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5416 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5417 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5418 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5419 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5420 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5421 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5422 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5423 + #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5424 + #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5425 + //MMVM_CONTEXT7_CNTL 5426 + #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5427 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5428 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5429 + #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5430 + #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5431 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5432 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5433 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5434 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5435 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5436 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5437 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5438 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5439 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5440 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5441 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5442 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5443 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5444 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5445 + #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5446 + #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5447 + #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5448 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5449 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5450 + #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5451 + #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5452 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5453 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5454 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5455 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5456 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5457 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5458 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5459 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5460 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5461 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5462 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5463 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5464 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5465 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5466 + #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5467 + #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5468 + //MMVM_CONTEXT8_CNTL 5469 + #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5470 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5471 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5472 + #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5473 + #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5474 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5475 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5476 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5477 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5478 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5479 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5480 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5481 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5482 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5483 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5484 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5485 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5486 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5487 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5488 + #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5489 + #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5490 + #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5491 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5492 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5493 + #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5494 + #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5495 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5496 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5497 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5498 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5499 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5500 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5501 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5502 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5503 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5504 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5505 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5506 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5507 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5508 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5509 + #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5510 + #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5511 + //MMVM_CONTEXT9_CNTL 5512 + #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5513 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5514 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5515 + #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5516 + #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5517 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5518 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5519 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5520 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5521 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5522 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5523 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5524 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5525 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5526 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5527 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5528 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5529 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5530 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5531 + #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5532 + #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5533 + #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5534 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5535 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5536 + #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5537 + #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5538 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5539 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5540 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5541 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5542 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5543 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5544 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5545 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5546 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5547 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5548 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5549 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5550 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5551 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5552 + #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5553 + #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5554 + //MMVM_CONTEXT10_CNTL 5555 + #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5556 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5557 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5558 + #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5559 + #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5560 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5561 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5562 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5563 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5564 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5565 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5566 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5567 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5568 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5569 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5570 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5571 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5572 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5573 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5574 + #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5575 + #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5576 + #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5577 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5578 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5579 + #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5580 + #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5581 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5582 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5583 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5584 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5585 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5586 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5587 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5588 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5589 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5590 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5591 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5592 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5593 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5594 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5595 + #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5596 + #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5597 + //MMVM_CONTEXT11_CNTL 5598 + #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5599 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5600 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5601 + #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5602 + #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5603 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5604 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5605 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5606 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5607 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5608 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5609 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5610 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5611 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5612 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5613 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5614 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5615 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5616 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5617 + #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5618 + #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5619 + #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5620 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5621 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5622 + #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5623 + #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5624 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5625 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5626 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5627 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5628 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5629 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5630 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5631 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5632 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5633 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5634 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5635 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5636 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5637 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5638 + #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5639 + #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5640 + //MMVM_CONTEXT12_CNTL 5641 + #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5642 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5643 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5644 + #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5645 + #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5646 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5647 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5648 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5649 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5650 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5651 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5652 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5653 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5654 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5655 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5656 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5657 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5658 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5659 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5660 + #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5661 + #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5662 + #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5663 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5664 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5665 + #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5666 + #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5667 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5668 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5669 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5670 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5671 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5672 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5673 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5674 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5675 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5676 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5677 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5678 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5679 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5680 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5681 + #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5682 + #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5683 + //MMVM_CONTEXT13_CNTL 5684 + #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5685 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5686 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5687 + #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5688 + #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5689 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5690 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5691 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5692 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5693 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5694 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5695 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5696 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5697 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5698 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5699 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5700 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5701 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5702 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5703 + #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5704 + #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5705 + #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5706 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5707 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5708 + #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5709 + #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5710 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5711 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5712 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5713 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5714 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5715 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5716 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5717 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5718 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5719 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5720 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5721 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5722 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5723 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5724 + #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5725 + #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5726 + //MMVM_CONTEXT14_CNTL 5727 + #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5728 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5729 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5730 + #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5731 + #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5732 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5733 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5734 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5735 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5736 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5737 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5738 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5739 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5740 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5741 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5742 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5743 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5744 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5745 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5746 + #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5747 + #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5748 + #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5749 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5750 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5751 + #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5752 + #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5753 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5754 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5755 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5756 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5757 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5758 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5759 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5760 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5761 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5762 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5763 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5764 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5765 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5766 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5767 + #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5768 + #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5769 + //MMVM_CONTEXT15_CNTL 5770 + #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5771 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5772 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5773 + #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5774 + #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5775 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5776 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5777 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5778 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5779 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5780 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5781 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5782 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5783 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5784 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5785 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5786 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5787 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5788 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5789 + #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 5790 + #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 5791 + #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5792 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5793 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5794 + #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5795 + #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5796 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5797 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5798 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5799 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5800 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5801 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5802 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5803 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5804 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5805 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5806 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5807 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5808 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5809 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5810 + #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 5811 + #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 5812 + //MMVM_CONTEXTS_DISABLE 5813 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5814 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5815 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5816 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5817 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5818 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5819 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5820 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5821 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5822 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5823 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5824 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5825 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5826 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5827 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5828 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5829 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5830 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5831 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5832 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5833 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5834 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5835 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5836 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5837 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5838 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5839 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5840 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5841 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5842 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5843 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5844 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5845 + //MMVM_INVALIDATE_ENG0_SEM 5846 + #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5847 + #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5848 + //MMVM_INVALIDATE_ENG1_SEM 5849 + #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5850 + #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5851 + //MMVM_INVALIDATE_ENG2_SEM 5852 + #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5853 + #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5854 + //MMVM_INVALIDATE_ENG3_SEM 5855 + #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5856 + #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5857 + //MMVM_INVALIDATE_ENG4_SEM 5858 + #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5859 + #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5860 + //MMVM_INVALIDATE_ENG5_SEM 5861 + #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5862 + #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5863 + //MMVM_INVALIDATE_ENG6_SEM 5864 + #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5865 + #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5866 + //MMVM_INVALIDATE_ENG7_SEM 5867 + #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5868 + #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5869 + //MMVM_INVALIDATE_ENG8_SEM 5870 + #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5871 + #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5872 + //MMVM_INVALIDATE_ENG9_SEM 5873 + #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5874 + #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5875 + //MMVM_INVALIDATE_ENG10_SEM 5876 + #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5877 + #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5878 + //MMVM_INVALIDATE_ENG11_SEM 5879 + #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5880 + #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5881 + //MMVM_INVALIDATE_ENG12_SEM 5882 + #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5883 + #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 5884 + //MMVM_INVALIDATE_ENG13_SEM 5885 + #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 5886 + #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 5887 + //MMVM_INVALIDATE_ENG14_SEM 5888 + #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 5889 + #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 5890 + //MMVM_INVALIDATE_ENG15_SEM 5891 + #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 5892 + #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 5893 + //MMVM_INVALIDATE_ENG16_SEM 5894 + #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 5895 + #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 5896 + //MMVM_INVALIDATE_ENG17_SEM 5897 + #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 5898 + #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 5899 + //MMVM_INVALIDATE_ENG0_REQ 5900 + #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5901 + #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 5902 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5903 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5904 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5905 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5906 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5907 + #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5908 + #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 5909 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5910 + #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5911 + #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 5912 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5913 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5914 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5915 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5916 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5917 + #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5918 + #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 5919 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5920 + //MMVM_INVALIDATE_ENG1_REQ 5921 + #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5922 + #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 5923 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5924 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5925 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5926 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5927 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5928 + #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5929 + #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 5930 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5931 + #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5932 + #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 5933 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5934 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5935 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5936 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5937 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5938 + #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5939 + #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 5940 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5941 + //MMVM_INVALIDATE_ENG2_REQ 5942 + #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5943 + #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 5944 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5945 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5946 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5947 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5948 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5949 + #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5950 + #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 5951 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5952 + #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5953 + #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 5954 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5955 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5956 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5957 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5958 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5959 + #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5960 + #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 5961 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5962 + //MMVM_INVALIDATE_ENG3_REQ 5963 + #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5964 + #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 5965 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5966 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5967 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5968 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5969 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5970 + #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5971 + #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 5972 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5973 + #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5974 + #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 5975 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5976 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5977 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5978 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5979 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5980 + #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5981 + #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 5982 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5983 + //MMVM_INVALIDATE_ENG4_REQ 5984 + #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5985 + #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 5986 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5987 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5988 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5989 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5990 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5991 + #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5992 + #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 5993 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5994 + #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5995 + #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 5996 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5997 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5998 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5999 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6000 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6001 + #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6002 + #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 6003 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6004 + //MMVM_INVALIDATE_ENG5_REQ 6005 + #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6006 + #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 6007 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6008 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6009 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6010 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6011 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6012 + #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6013 + #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 6014 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6015 + #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6016 + #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 6017 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6018 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6019 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6020 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6021 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6022 + #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6023 + #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 6024 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6025 + //MMVM_INVALIDATE_ENG6_REQ 6026 + #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6027 + #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 6028 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6029 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6030 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6031 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6032 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6033 + #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6034 + #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 6035 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6036 + #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6037 + #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 6038 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6039 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6040 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6041 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6042 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6043 + #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6044 + #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 6045 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6046 + //MMVM_INVALIDATE_ENG7_REQ 6047 + #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6048 + #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 6049 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6050 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6051 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6052 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6053 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6054 + #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6055 + #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 6056 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6057 + #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6058 + #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 6059 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6060 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6061 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6062 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6063 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6064 + #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6065 + #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 6066 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6067 + //MMVM_INVALIDATE_ENG8_REQ 6068 + #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6069 + #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 6070 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6071 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6072 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6073 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6074 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6075 + #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6076 + #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 6077 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6078 + #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6079 + #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 6080 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6081 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6082 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6083 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6084 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6085 + #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6086 + #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 6087 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6088 + //MMVM_INVALIDATE_ENG9_REQ 6089 + #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6090 + #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 6091 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6092 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6093 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6094 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6095 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6096 + #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6097 + #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 6098 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6099 + #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6100 + #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6101 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6102 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6103 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6104 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6105 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6106 + #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6107 + #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6108 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6109 + //MMVM_INVALIDATE_ENG10_REQ 6110 + #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6111 + #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6112 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6113 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6114 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6115 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6116 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6117 + #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6118 + #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6119 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6120 + #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6121 + #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6122 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6123 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6124 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6125 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6126 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6127 + #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6128 + #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6129 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6130 + //MMVM_INVALIDATE_ENG11_REQ 6131 + #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6132 + #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6133 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6134 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6135 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6136 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6137 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6138 + #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6139 + #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6140 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6141 + #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6142 + #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6143 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6144 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6145 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6146 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6147 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6148 + #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6149 + #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6150 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6151 + //MMVM_INVALIDATE_ENG12_REQ 6152 + #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6153 + #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6154 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6155 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6156 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6157 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6158 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6159 + #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6160 + #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6161 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6162 + #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6163 + #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6164 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6165 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6166 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6167 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6168 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6169 + #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6170 + #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6171 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6172 + //MMVM_INVALIDATE_ENG13_REQ 6173 + #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6174 + #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6175 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6176 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6177 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6178 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6179 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6180 + #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6181 + #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6182 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6183 + #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6184 + #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6185 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6186 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6187 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6188 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6189 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6190 + #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6191 + #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6192 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6193 + //MMVM_INVALIDATE_ENG14_REQ 6194 + #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6195 + #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6196 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6197 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6198 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6199 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6200 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6201 + #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6202 + #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6203 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6204 + #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6205 + #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6206 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6207 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6208 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6209 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6210 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6211 + #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6212 + #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6213 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6214 + //MMVM_INVALIDATE_ENG15_REQ 6215 + #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6216 + #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6217 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6218 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6219 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6220 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6221 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6222 + #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6223 + #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6224 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6225 + #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6226 + #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6227 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6228 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6229 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6230 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6231 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6232 + #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6233 + #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6234 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6235 + //MMVM_INVALIDATE_ENG16_REQ 6236 + #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6237 + #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6238 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6239 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6240 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6241 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6242 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6243 + #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6244 + #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6245 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6246 + #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6247 + #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6248 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6249 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6250 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6251 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6252 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6253 + #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6254 + #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6255 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6256 + //MMVM_INVALIDATE_ENG17_REQ 6257 + #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6258 + #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6259 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6260 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6261 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6262 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6263 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6264 + #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6265 + #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6266 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6267 + #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6268 + #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6269 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6270 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6271 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6272 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6273 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6274 + #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6275 + #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6276 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6277 + //MMVM_INVALIDATE_ENG0_ACK 6278 + #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6279 + #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6280 + #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6281 + #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6282 + //MMVM_INVALIDATE_ENG1_ACK 6283 + #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6284 + #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6285 + #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6286 + #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6287 + //MMVM_INVALIDATE_ENG2_ACK 6288 + #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6289 + #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6290 + #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6291 + #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6292 + //MMVM_INVALIDATE_ENG3_ACK 6293 + #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6294 + #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6295 + #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6296 + #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6297 + //MMVM_INVALIDATE_ENG4_ACK 6298 + #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6299 + #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6300 + #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6301 + #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6302 + //MMVM_INVALIDATE_ENG5_ACK 6303 + #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6304 + #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6305 + #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6306 + #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6307 + //MMVM_INVALIDATE_ENG6_ACK 6308 + #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6309 + #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6310 + #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6311 + #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6312 + //MMVM_INVALIDATE_ENG7_ACK 6313 + #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6314 + #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6315 + #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6316 + #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6317 + //MMVM_INVALIDATE_ENG8_ACK 6318 + #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6319 + #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6320 + #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6321 + #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6322 + //MMVM_INVALIDATE_ENG9_ACK 6323 + #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6324 + #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6325 + #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6326 + #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6327 + //MMVM_INVALIDATE_ENG10_ACK 6328 + #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6329 + #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6330 + #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6331 + #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6332 + //MMVM_INVALIDATE_ENG11_ACK 6333 + #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6334 + #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6335 + #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6336 + #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6337 + //MMVM_INVALIDATE_ENG12_ACK 6338 + #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6339 + #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6340 + #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6341 + #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6342 + //MMVM_INVALIDATE_ENG13_ACK 6343 + #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6344 + #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6345 + #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6346 + #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6347 + //MMVM_INVALIDATE_ENG14_ACK 6348 + #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6349 + #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6350 + #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6351 + #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6352 + //MMVM_INVALIDATE_ENG15_ACK 6353 + #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6354 + #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6355 + #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6356 + #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6357 + //MMVM_INVALIDATE_ENG16_ACK 6358 + #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6359 + #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6360 + #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6361 + #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6362 + //MMVM_INVALIDATE_ENG17_ACK 6363 + #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6364 + #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6365 + #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6366 + #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6367 + //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6368 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6369 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6370 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6371 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6372 + //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6373 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6374 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6375 + //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6376 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6377 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6378 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6379 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6380 + //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6381 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6382 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6383 + //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6384 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6385 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6386 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6387 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6388 + //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6389 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6390 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6391 + //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6392 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6393 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6394 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6395 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6396 + //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6397 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6398 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6399 + //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6400 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6401 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6402 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6403 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6404 + //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6405 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6406 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6407 + //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6408 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6409 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6410 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6411 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6412 + //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6413 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6414 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6415 + //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6416 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6417 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6418 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6419 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6420 + //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6421 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6422 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6423 + //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6424 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6425 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6426 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6427 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6428 + //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6429 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6430 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6431 + //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6432 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6433 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6434 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6435 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6436 + //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6437 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6438 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6439 + //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6440 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6441 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6442 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6443 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6444 + //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6445 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6446 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6447 + //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6448 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6449 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6450 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6451 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6452 + //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6453 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6454 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6455 + //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6456 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6457 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6458 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6459 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6460 + //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6461 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6462 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6463 + //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6464 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6465 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6466 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6467 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6468 + //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6469 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6470 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6471 + //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6472 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6473 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6474 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6475 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6476 + //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6477 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6478 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6479 + //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6480 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6481 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6482 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6483 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6484 + //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6485 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6486 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6487 + //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6488 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6489 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6490 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6491 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6492 + //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6493 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6494 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6495 + //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6496 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6497 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6498 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6499 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6500 + //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6501 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6502 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6503 + //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6504 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6505 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6506 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6507 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6508 + //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6509 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6510 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6511 + //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6512 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6513 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6514 + //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6515 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6516 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6517 + //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6518 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6519 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6520 + //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6521 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6522 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6523 + //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6524 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6525 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6526 + //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6527 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6528 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6529 + //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6530 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6531 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6532 + //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6533 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6534 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6535 + //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6536 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6537 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6538 + //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6539 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6540 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6541 + //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6542 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6543 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6544 + //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6545 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6546 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6547 + //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6548 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6549 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6550 + //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6551 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6552 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6553 + //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6554 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6555 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6556 + //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6557 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6558 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6559 + //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6560 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6561 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6562 + //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6563 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6564 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6565 + //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6566 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6567 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6568 + //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6569 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6570 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6571 + //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6572 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6573 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6574 + //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6575 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6576 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6577 + //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6578 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6579 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6580 + //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6581 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6582 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6583 + //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6584 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6585 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6586 + //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6587 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6588 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6589 + //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6590 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6591 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6592 + //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6593 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6594 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6595 + //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6596 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6597 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6598 + //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6599 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6600 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6601 + //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6602 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6603 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6604 + //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6605 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6606 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6607 + //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6608 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6609 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6610 + //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6611 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6612 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6613 + //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6614 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6615 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6616 + //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6617 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6618 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6619 + //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6620 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6621 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6622 + //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6623 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6624 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6625 + //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6626 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6627 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6628 + //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6629 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6630 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6631 + //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6632 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6633 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6634 + //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6635 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6636 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6637 + //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6638 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6639 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6640 + //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6641 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6642 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6643 + //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6644 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6645 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6646 + //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6647 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6648 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6649 + //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6650 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6651 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6652 + //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6653 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6654 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6655 + //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6656 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6657 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6658 + //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6659 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6660 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6661 + //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6662 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6663 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6664 + //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6665 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6666 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6667 + //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6668 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6669 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6670 + //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6671 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6672 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6673 + //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6674 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6675 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6676 + //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6677 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6678 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6679 + //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6680 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6681 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6682 + //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6683 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6684 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6685 + //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6686 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6687 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6688 + //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6689 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6690 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6691 + //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6692 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6693 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6694 + //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6695 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6696 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6697 + //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6698 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6699 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6700 + //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6701 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6702 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6703 + //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6704 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6705 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6706 + //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6707 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6708 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6709 + //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6710 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6711 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6712 + //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6713 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6714 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6715 + //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6716 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6717 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6718 + //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6719 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6720 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6721 + //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6722 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6723 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6724 + //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6725 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6726 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6727 + //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6728 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6729 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6730 + //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6731 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6732 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6733 + //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6734 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6735 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6736 + //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6737 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6738 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6739 + //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6740 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6741 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6742 + //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6743 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6744 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6745 + //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6746 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6747 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6748 + //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6749 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6750 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6751 + //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6752 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6753 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6754 + //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6755 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6756 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6757 + //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6758 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6759 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6760 + //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6761 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6762 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6763 + //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6764 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6765 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6766 + //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6767 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6768 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6769 + //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6770 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6771 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6772 + //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6773 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6774 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6775 + //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6776 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6777 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6778 + //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6779 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6780 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6781 + //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6782 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6783 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6784 + //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6785 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6786 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6787 + //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6788 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6789 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6790 + //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6791 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6792 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6793 + //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6794 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6795 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6796 + //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6797 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6798 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6799 + //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6800 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6801 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6802 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6803 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6804 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6805 + #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6806 + //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6807 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6808 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6809 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6810 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6811 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6812 + #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6813 + //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6814 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6815 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6816 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6817 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6818 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6819 + #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6820 + //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6821 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6822 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6823 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6824 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6825 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6826 + #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6827 + //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6828 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6829 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6830 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6831 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6832 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6833 + #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6834 + //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6835 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6836 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6837 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6838 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6839 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6840 + #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6841 + //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6842 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6843 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6844 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6845 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6846 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6847 + #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6848 + //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6849 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6850 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6851 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6852 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6853 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6854 + #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6855 + //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6856 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6857 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6858 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6859 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6860 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6861 + #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6862 + //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6863 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6864 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6865 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6866 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6867 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6868 + #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6869 + //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6870 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6871 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6872 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6873 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6874 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6875 + #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6876 + //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6877 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6878 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6879 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6880 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6881 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6882 + #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6883 + //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6884 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6885 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6886 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6887 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6888 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6889 + #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6890 + //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6891 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6892 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6893 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6894 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6895 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6896 + #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6897 + //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6898 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6899 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6900 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6901 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6902 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6903 + #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6904 + //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6905 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6906 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6907 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6908 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6909 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6910 + #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6911 + //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6912 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6913 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6914 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6915 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6916 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6917 + #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6918 + 6919 + 6920 + // addressBlock: mmhub_mmutcl2_mmvml2pldec 6921 + //MMMC_VM_L2_PERFCOUNTER0_CFG 6922 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6923 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6924 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6925 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6926 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6927 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6928 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6929 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6930 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6931 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6932 + //MMMC_VM_L2_PERFCOUNTER1_CFG 6933 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6934 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6935 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6936 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6937 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6938 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6939 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6940 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6941 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6942 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6943 + //MMMC_VM_L2_PERFCOUNTER2_CFG 6944 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6945 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6946 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6947 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6948 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6949 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6950 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6951 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6952 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6953 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6954 + //MMMC_VM_L2_PERFCOUNTER3_CFG 6955 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6956 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6957 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6958 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6959 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6960 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6961 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6962 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6963 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6964 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6965 + //MMMC_VM_L2_PERFCOUNTER4_CFG 6966 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6967 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6968 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6969 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6970 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6971 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6972 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6973 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6974 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6975 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6976 + //MMMC_VM_L2_PERFCOUNTER5_CFG 6977 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6978 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6979 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6980 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6981 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6982 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6983 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6984 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6985 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6986 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6987 + //MMMC_VM_L2_PERFCOUNTER6_CFG 6988 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6989 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6990 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6991 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6992 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6993 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6994 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6995 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6996 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6997 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6998 + //MMMC_VM_L2_PERFCOUNTER7_CFG 6999 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 7000 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 7001 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 7002 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 7003 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 7004 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 7005 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 7006 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 7007 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 7008 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 7009 + //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 7010 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7011 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7012 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7013 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7014 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7015 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7016 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7017 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7018 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7019 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7020 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7021 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7022 + //MMUTCL2_PERFCOUNTER0_CFG 7023 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7024 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7025 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7026 + #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7027 + #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7028 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7029 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7030 + #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7031 + #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7032 + #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7033 + //MMUTCL2_PERFCOUNTER1_CFG 7034 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7035 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7036 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7037 + #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7038 + #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7039 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7040 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7041 + #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7042 + #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7043 + #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7044 + //MMUTCL2_PERFCOUNTER2_CFG 7045 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7046 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7047 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7048 + #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7049 + #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7050 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7051 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7052 + #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7053 + #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7054 + #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7055 + //MMUTCL2_PERFCOUNTER3_CFG 7056 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7057 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7058 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7059 + #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7060 + #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7061 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7062 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7063 + #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7064 + #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7065 + #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7066 + //MMUTCL2_PERFCOUNTER_RSLT_CNTL 7067 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7068 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7069 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7070 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7071 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7072 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7073 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7074 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7075 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7076 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7077 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7078 + #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7079 + 7080 + 7081 + // addressBlock: mmhub_mmutcl2_mmvml2prdec 7082 + //MMMC_VM_L2_PERFCOUNTER_LO 7083 + #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7084 + #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7085 + //MMMC_VM_L2_PERFCOUNTER_HI 7086 + #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7087 + #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7088 + #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7089 + #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7090 + //MMUTCL2_PERFCOUNTER_LO 7091 + #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7092 + #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7093 + //MMUTCL2_PERFCOUNTER_HI 7094 + #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7095 + #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7096 + #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7097 + #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7098 + 7099 + 7100 + // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 7101 + //MMVM_PCIE_ATS_CNTL 7102 + #define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 7103 + #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 7104 + #define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 7105 + #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 7106 + 7107 + 7108 + // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 7109 + //MMMC_VM_NB_MMIOBASE 7110 + #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 7111 + #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 7112 + //MMMC_VM_NB_MMIOLIMIT 7113 + #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 7114 + #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 7115 + //MMMC_VM_NB_PCI_CTRL 7116 + #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 7117 + #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 7118 + //MMMC_VM_NB_PCI_ARB 7119 + #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 7120 + #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 7121 + //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 7122 + #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 7123 + #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 7124 + //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 7125 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 7126 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 7127 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 7128 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 7129 + //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 7130 + #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 7131 + #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 7132 + //MMMC_VM_FB_OFFSET 7133 + #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 7134 + #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 7135 + //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 7136 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 7137 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 7138 + //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 7139 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 7140 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 7141 + //MMMC_VM_STEERING 7142 + #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 7143 + #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 7144 + //MMMC_SHARED_VIRT_RESET_REQ 7145 + #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 7146 + #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 7147 + #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 7148 + #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 7149 + //MMMC_MEM_POWER_LS 7150 + #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7151 + #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7152 + #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7153 + #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7154 + //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 7155 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 7156 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7157 + //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 7158 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 7159 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7160 + //MMMC_VM_LOCAL_SYSMEM_ADDRESS_START 7161 + #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 7162 + #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7163 + //MMMC_VM_LOCAL_SYSMEM_ADDRESS_END 7164 + #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 7165 + #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7166 + //MMMC_VM_APT_CNTL 7167 + #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 7168 + #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 7169 + #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 7170 + #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 7171 + #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 7172 + #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 7173 + #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 7174 + #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 7175 + #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 7176 + #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L 7177 + #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L 7178 + #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L 7179 + //MMMC_VM_LOCAL_FB_ADDRESS_START 7180 + #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 7181 + #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7182 + //MMMC_VM_LOCAL_FB_ADDRESS_END 7183 + #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 7184 + #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7185 + //MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 7186 + #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 7187 + #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 7188 + //MMUTCL2_CGTT_CLK_CTRL 7189 + #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7190 + #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 7191 + #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 7192 + #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 7193 + #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 7194 + #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 7195 + #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 7196 + #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 7197 + #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 7198 + #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 7199 + //MMMC_SHARED_ACTIVE_FCN_ID 7200 + #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 7201 + #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1e 7202 + #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 7203 + #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x40000000L 7204 + //MMUTCL2_CGTT_BUSY_CTRL 7205 + #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 7206 + #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 7207 + #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 7208 + #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 7209 + //MMUTCL2_HARVEST_BYPASS_GROUPS 7210 + #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 7211 + #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 7212 + //MMUTCL2_GROUP_RET_FAULT_STATUS 7213 + #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 7214 + #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL 7215 + 7216 + 7217 + // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 7218 + //MMMC_VM_FB_LOCATION_BASE 7219 + #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 7220 + #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 7221 + //MMMC_VM_FB_LOCATION_TOP 7222 + #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 7223 + #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 7224 + //MMMC_VM_AGP_TOP 7225 + #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 7226 + #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 7227 + //MMMC_VM_AGP_BOT 7228 + #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 7229 + #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 7230 + //MMMC_VM_AGP_BASE 7231 + #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 7232 + #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 7233 + //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 7234 + #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 7235 + #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7236 + //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 7237 + #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 7238 + #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7239 + //MMMC_VM_MX_L1_TLB_CNTL 7240 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 7241 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 7242 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 7243 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 7244 + #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 7245 + #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 7246 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 7247 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 7248 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 7249 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 7250 + #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 7251 + #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 7252 + 7253 + 7254 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 7255 + //MM_ATC_L2_PERFCOUNTER_LO 7256 + #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7257 + #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7258 + //MM_ATC_L2_PERFCOUNTER_HI 7259 + #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7260 + #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7261 + #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7262 + #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7263 + 7264 + 7265 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 7266 + //MM_ATC_L2_PERFCOUNTER0_CFG 7267 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7268 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7269 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7270 + #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7271 + #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7272 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7273 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7274 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7275 + #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7276 + #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7277 + //MM_ATC_L2_PERFCOUNTER1_CFG 7278 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7279 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7280 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7281 + #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7282 + #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7283 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7284 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7285 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7286 + #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7287 + #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7288 + //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 7289 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7290 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7291 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7292 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7293 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7294 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7295 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7296 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7297 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7298 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7299 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7300 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7301 + 7302 + 7303 + // addressBlock: mmhub_mmutcl2_mmvml2pspdec 7304 + //MMUTCL2_TRANSLATION_BYPASS_BY_VMID 7305 + #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 7306 + #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 7307 + #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL 7308 + #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L 7309 + //MMVM_IOMMU_CONTROL_REGISTER 7310 + #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 7311 + #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 7312 + //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 7313 + #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 7314 + #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 7315 + //MMUTC_TRANSLATION_FAULT_CNTL0 7316 + #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 7317 + #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL 7318 + //MMUTC_TRANSLATION_FAULT_CNTL1 7319 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 7320 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 7321 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 7322 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 7323 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL 7324 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L 7325 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L 7326 + #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L 7327 + 7328 + 7329 + // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 7330 + //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 7331 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 7332 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L 7333 + 7334 + 7335 + // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 7336 + //MM_ATC_L2_IOV_MODE_CNTL 7337 + #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0 7338 + #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L 7339 + 7340 + 7341 + // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 7342 + //MML2TLB_TLB0_STATUS 7343 + #define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 7344 + #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7345 + #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 7346 + #define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L 7347 + #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7348 + #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 7349 + //MML2TLB_TMZ_CNTL 7350 + #define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 7351 + #define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L 7352 + //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 7353 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 7354 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL 7355 + //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 7356 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 7357 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 7358 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 7359 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc 7360 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd 7361 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf 7362 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 7363 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 7364 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 7365 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e 7366 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL 7367 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L 7368 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L 7369 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L 7370 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L 7371 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L 7372 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L 7373 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L 7374 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L 7375 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L 7376 + //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 7377 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 7378 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL 7379 + //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 7380 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 7381 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 7382 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 7383 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd 7384 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe 7385 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf 7386 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 7387 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 7388 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 7389 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 7390 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 7391 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 7392 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f 7393 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL 7394 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L 7395 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L 7396 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L 7397 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L 7398 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L 7399 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L 7400 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L 7401 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L 7402 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L 7403 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L 7404 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L 7405 + #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L 7406 + //MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 7407 + #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 7408 + #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa 7409 + #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 7410 + #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L 7411 + 7412 + 7413 + // addressBlock: mmhub_mmutcl2_mml2tlbpldec 7414 + //MML2TLB_PERFCOUNTER0_CFG 7415 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7416 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7417 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7418 + #define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7419 + #define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7420 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7421 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7422 + #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7423 + #define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7424 + #define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7425 + //MML2TLB_PERFCOUNTER1_CFG 7426 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7427 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7428 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7429 + #define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7430 + #define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7431 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7432 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7433 + #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7434 + #define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7435 + #define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7436 + //MML2TLB_PERFCOUNTER2_CFG 7437 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7438 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7439 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7440 + #define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7441 + #define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7442 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7443 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7444 + #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7445 + #define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7446 + #define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7447 + //MML2TLB_PERFCOUNTER3_CFG 7448 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7449 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7450 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7451 + #define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7452 + #define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7453 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7454 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7455 + #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7456 + #define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7457 + #define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7458 + //MML2TLB_PERFCOUNTER_RSLT_CNTL 7459 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7460 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7461 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7462 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7463 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7464 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7465 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7466 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7467 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7468 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7469 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7470 + #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7471 + 7472 + 7473 + // addressBlock: mmhub_mmutcl2_mml2tlbprdec 7474 + //MML2TLB_PERFCOUNTER_LO 7475 + #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7476 + #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7477 + //MML2TLB_PERFCOUNTER_HI 7478 + #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7479 + #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7480 + #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7481 + #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7482 + 7483 + #endif