Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: use the callback function for reset status polling on IMU

Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.

v2: drop unused variable (Alex)

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Huang Rui and committed by
Alex Deucher
16600b7d 9fe5d08f

+24 -14
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
··· 35 35 void (*setup_imu)(struct amdgpu_device *adev); 36 36 int (*start_imu)(struct amdgpu_device *adev); 37 37 void (*program_rlc_ram)(struct amdgpu_device *adev); 38 + int (*wait_for_reset_status)(struct amdgpu_device *adev); 38 39 }; 39 40 40 41 struct imu_rlc_ram_golden {
+23 -14
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
··· 117 117 return 0; 118 118 } 119 119 120 + static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev) 121 + { 122 + int i, imu_reg_val = 0; 123 + 124 + for (i = 0; i < adev->usec_timeout; i++) { 125 + imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); 126 + if ((imu_reg_val & 0x1f) == 0x1f) 127 + break; 128 + udelay(1); 129 + } 130 + 131 + if (i >= adev->usec_timeout) { 132 + dev_err(adev->dev, "init imu: IMU start timeout\n"); 133 + return -ETIMEDOUT; 134 + } 135 + 136 + return 0; 137 + } 138 + 120 139 static void imu_v11_0_setup(struct amdgpu_device *adev) 121 140 { 122 141 int imu_reg_val; ··· 158 139 159 140 static int imu_v11_0_start(struct amdgpu_device *adev) 160 141 { 161 - int imu_reg_val, i; 142 + int imu_reg_val; 162 143 163 144 //Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0 164 145 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); 165 146 imu_reg_val &= 0xfffffffe; 166 147 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); 167 148 168 - if (adev->gfx.imu.mode == DEBUG_MODE) { 169 - for (i = 0; i < adev->usec_timeout; i++) { 170 - imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); 171 - if ((imu_reg_val & 0x1f) == 0x1f) 172 - break; 173 - udelay(1); 174 - } 175 - 176 - if (i >= adev->usec_timeout) { 177 - dev_err(adev->dev, "init imu: IMU start timeout\n"); 178 - return -ETIMEDOUT; 179 - } 180 - } 149 + if (adev->gfx.imu.mode == DEBUG_MODE) 150 + return imu_v11_0_wait_for_reset_status(adev); 181 151 182 152 return 0; 183 153 } ··· 376 368 .setup_imu = imu_v11_0_setup, 377 369 .start_imu = imu_v11_0_start, 378 370 .program_rlc_ram = imu_v11_0_program_rlc_ram, 371 + .wait_for_reset_status = imu_v11_0_wait_for_reset_status, 379 372 };