Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: rename amdgpu_dpm_funcs to amd_pm_funcs

renamed amdgpu_dpm_funcs and moved to amd_shared.h
so can shared with powerplay.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
cfa289fd 698f88e6

+201 -129
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
··· 960 960 } 961 961 962 962 struct amd_vce_state* 963 - amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx) 963 + amdgpu_get_vce_clock_state(void *handle, u32 idx) 964 964 { 965 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 966 + 965 967 if (idx < adev->pm.dpm.num_of_vce_states) 966 968 return &adev->pm.dpm.vce_states[idx]; 967 969
+2 -45
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
··· 241 241 AMDGPU_PCIE_GEN_INVALID = 0xffff 242 242 }; 243 243 244 - struct amdgpu_dpm_funcs { 245 - int (*get_temperature)(struct amdgpu_device *adev); 246 - int (*pre_set_power_state)(struct amdgpu_device *adev); 247 - int (*set_power_state)(struct amdgpu_device *adev); 248 - void (*post_set_power_state)(struct amdgpu_device *adev); 249 - void (*display_configuration_changed)(struct amdgpu_device *adev); 250 - u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 251 - u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 252 - void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 253 - void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 254 - int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level); 255 - bool (*vblank_too_short)(struct amdgpu_device *adev); 256 - void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 257 - void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 258 - void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 259 - void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 260 - u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 261 - int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 262 - int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 263 - int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); 264 - int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); 265 - int (*get_sclk_od)(struct amdgpu_device *adev); 266 - int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); 267 - int (*get_mclk_od)(struct amdgpu_device *adev); 268 - int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); 269 - int (*check_state_equal)(struct amdgpu_device *adev, 270 - struct amdgpu_ps *cps, 271 - struct amdgpu_ps *rps, 272 - bool *equal); 273 - int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value, 274 - int *size); 275 - 276 - struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx); 277 - int (*reset_power_profile_state)(struct amdgpu_device *adev, 278 - struct amd_pp_profile *request); 279 - int (*get_power_profile_state)(struct amdgpu_device *adev, 280 - struct amd_pp_profile *query); 281 - int (*set_power_profile_state)(struct amdgpu_device *adev, 282 - struct amd_pp_profile *request); 283 - int (*switch_power_profile)(struct amdgpu_device *adev, 284 - enum amd_pp_profile_type type); 285 - }; 286 - 287 244 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 288 245 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 289 246 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) ··· 442 485 struct amdgpu_dpm dpm; 443 486 const struct firmware *fw; /* SMC firmware */ 444 487 uint32_t fw_version; 445 - const struct amdgpu_dpm_funcs *funcs; 488 + const struct amd_pm_funcs *funcs; 446 489 uint32_t pcie_gen_mask; 447 490 uint32_t pcie_mlw_mask; 448 491 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ ··· 508 551 u8 amdgpu_encode_pci_lane_width(u32 lanes); 509 552 510 553 struct amd_vce_state* 511 - amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx); 554 + amdgpu_get_vce_clock_state(void *handle, u32 idx); 512 555 513 556 #endif
+66 -34
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
··· 883 883 return ret; 884 884 } 885 885 886 - static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) 886 + static void ci_dpm_powergate_uvd(void *handle, bool gate) 887 887 { 888 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 888 889 struct ci_power_info *pi = ci_get_pi(adev); 889 890 890 891 pi->uvd_power_gated = gate; ··· 902 901 } 903 902 } 904 903 905 - static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) 904 + static bool ci_dpm_vblank_too_short(void *handle) 906 905 { 906 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 907 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 908 908 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; 909 909 ··· 1212 1210 } 1213 1211 } 1214 1212 1215 - static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev, 1213 + static int ci_dpm_get_fan_speed_percent(void *handle, 1216 1214 u32 *speed) 1217 1215 { 1218 1216 u32 duty, duty100; 1219 1217 u64 tmp64; 1218 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1219 1221 1220 if (adev->pm.no_fan) 1222 1221 return -ENOENT; ··· 1240 1237 return 0; 1241 1238 } 1242 1239 1243 - static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev, 1240 + static int ci_dpm_set_fan_speed_percent(void *handle, 1244 1241 u32 speed) 1245 1242 { 1246 1243 u32 tmp; 1247 1244 u32 duty, duty100; 1248 1245 u64 tmp64; 1246 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 1247 struct ci_power_info *pi = ci_get_pi(adev); 1250 1248 1251 1249 if (adev->pm.no_fan) ··· 1275 1271 return 0; 1276 1272 } 1277 1273 1278 - static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) 1274 + static void ci_dpm_set_fan_control_mode(void *handle, u32 mode) 1279 1275 { 1276 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 + 1280 1278 switch (mode) { 1281 1279 case AMD_FAN_CTRL_NONE: 1282 1280 if (adev->pm.dpm.fan.ucode_fan_control) ··· 1298 1292 } 1299 1293 } 1300 1294 1301 - static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev) 1295 + static u32 ci_dpm_get_fan_control_mode(void *handle) 1302 1296 { 1297 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1303 1298 struct ci_power_info *pi = ci_get_pi(adev); 1304 1299 1305 1300 if (pi->fan_is_controlled_by_smc) ··· 4385 4378 } 4386 4379 4387 4380 4388 - static int ci_dpm_force_performance_level(struct amdgpu_device *adev, 4381 + static int ci_dpm_force_performance_level(void *handle, 4389 4382 enum amd_dpm_forced_level level) 4390 4383 { 4384 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4391 4385 struct ci_power_info *pi = ci_get_pi(adev); 4392 4386 u32 tmp, levels, i; 4393 4387 int ret; ··· 5299 5291 adev->pm.dpm.requested_ps = &pi->requested_rps; 5300 5292 } 5301 5293 5302 - static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) 5294 + static int ci_dpm_pre_set_power_state(void *handle) 5303 5295 { 5296 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5304 5297 struct ci_power_info *pi = ci_get_pi(adev); 5305 5298 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 5306 5299 struct amdgpu_ps *new_ps = &requested_ps; ··· 5313 5304 return 0; 5314 5305 } 5315 5306 5316 - static void ci_dpm_post_set_power_state(struct amdgpu_device *adev) 5307 + static void ci_dpm_post_set_power_state(void *handle) 5317 5308 { 5309 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5318 5310 struct ci_power_info *pi = ci_get_pi(adev); 5319 5311 struct amdgpu_ps *new_ps = &pi->requested_rps; 5320 5312 ··· 5489 5479 ci_update_current_ps(adev, boot_ps); 5490 5480 } 5491 5481 5492 - static int ci_dpm_set_power_state(struct amdgpu_device *adev) 5482 + static int ci_dpm_set_power_state(void *handle) 5493 5483 { 5484 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5494 5485 struct ci_power_info *pi = ci_get_pi(adev); 5495 5486 struct amdgpu_ps *new_ps = &pi->requested_rps; 5496 5487 struct amdgpu_ps *old_ps = &pi->current_rps; ··· 5562 5551 } 5563 5552 #endif 5564 5553 5565 - static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev) 5554 + static void ci_dpm_display_configuration_changed(void *handle) 5566 5555 { 5556 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5557 + 5567 5558 ci_program_display_gap(adev); 5568 5559 } 5569 5560 ··· 6118 6105 } 6119 6106 6120 6107 static void 6121 - ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 6108 + ci_dpm_debugfs_print_current_performance_level(void *handle, 6122 6109 struct seq_file *m) 6123 6110 { 6111 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6124 6112 struct ci_power_info *pi = ci_get_pi(adev); 6125 6113 struct amdgpu_ps *rps = &pi->current_rps; 6126 6114 u32 sclk = ci_get_average_sclk_freq(adev); ··· 6145 6131 seq_printf(m, "GPU load: %u %%\n", activity_percent); 6146 6132 } 6147 6133 6148 - static void ci_dpm_print_power_state(struct amdgpu_device *adev, 6149 - struct amdgpu_ps *rps) 6134 + static void ci_dpm_print_power_state(void *handle, void *current_ps) 6150 6135 { 6136 + struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 6151 6137 struct ci_ps *ps = ci_get_ps(rps); 6152 6138 struct ci_pl *pl; 6153 6139 int i; 6140 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6154 6141 6155 6142 amdgpu_dpm_print_class_info(rps->class, rps->class2); 6156 6143 amdgpu_dpm_print_cap_info(rps->caps); ··· 6173 6158 (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane)); 6174 6159 } 6175 6160 6176 - static int ci_check_state_equal(struct amdgpu_device *adev, 6177 - struct amdgpu_ps *cps, 6178 - struct amdgpu_ps *rps, 6161 + static int ci_check_state_equal(void *handle, 6162 + void *current_ps, 6163 + void *request_ps, 6179 6164 bool *equal) 6180 6165 { 6181 6166 struct ci_ps *ci_cps; 6182 6167 struct ci_ps *ci_rps; 6183 6168 int i; 6169 + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 6170 + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 6171 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6184 6172 6185 6173 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 6186 6174 return -EINVAL; 6187 6175 6188 - ci_cps = ci_get_ps(cps); 6189 - ci_rps = ci_get_ps(rps); 6176 + ci_cps = ci_get_ps((struct amdgpu_ps *)cps); 6177 + ci_rps = ci_get_ps((struct amdgpu_ps *)rps); 6190 6178 6191 6179 if (ci_cps == NULL) { 6192 6180 *equal = false; ··· 6217 6199 return 0; 6218 6200 } 6219 6201 6220 - static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) 6202 + static u32 ci_dpm_get_sclk(void *handle, bool low) 6221 6203 { 6204 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6222 6205 struct ci_power_info *pi = ci_get_pi(adev); 6223 6206 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 6224 6207 ··· 6229 6210 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 6230 6211 } 6231 6212 6232 - static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low) 6213 + static u32 ci_dpm_get_mclk(void *handle, bool low) 6233 6214 { 6215 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6234 6216 struct ci_power_info *pi = ci_get_pi(adev); 6235 6217 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 6236 6218 ··· 6242 6222 } 6243 6223 6244 6224 /* get temperature in millidegrees */ 6245 - static int ci_dpm_get_temp(struct amdgpu_device *adev) 6225 + static int ci_dpm_get_temp(void *handle) 6246 6226 { 6247 6227 u32 temp; 6248 6228 int actual_temp = 0; 6229 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6249 6230 6250 6231 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 6251 6232 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; ··· 6572 6551 return 0; 6573 6552 } 6574 6553 6575 - static int ci_dpm_print_clock_levels(struct amdgpu_device *adev, 6554 + static int ci_dpm_print_clock_levels(void *handle, 6576 6555 enum pp_clock_type type, char *buf) 6577 6556 { 6557 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6578 6558 struct ci_power_info *pi = ci_get_pi(adev); 6579 6559 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 6580 6560 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; ··· 6640 6618 return size; 6641 6619 } 6642 6620 6643 - static int ci_dpm_force_clock_level(struct amdgpu_device *adev, 6621 + static int ci_dpm_force_clock_level(void *handle, 6644 6622 enum pp_clock_type type, uint32_t mask) 6645 6623 { 6624 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6646 6625 struct ci_power_info *pi = ci_get_pi(adev); 6647 6626 6648 6627 if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO | ··· 6687 6664 return 0; 6688 6665 } 6689 6666 6690 - static int ci_dpm_get_sclk_od(struct amdgpu_device *adev) 6667 + static int ci_dpm_get_sclk_od(void *handle) 6691 6668 { 6669 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6692 6670 struct ci_power_info *pi = ci_get_pi(adev); 6693 6671 struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table); 6694 6672 struct ci_single_dpm_table *golden_sclk_table = ··· 6704 6680 return value; 6705 6681 } 6706 6682 6707 - static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 6683 + static int ci_dpm_set_sclk_od(void *handle, uint32_t value) 6708 6684 { 6685 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6709 6686 struct ci_power_info *pi = ci_get_pi(adev); 6710 6687 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps); 6711 6688 struct ci_single_dpm_table *golden_sclk_table = ··· 6723 6698 return 0; 6724 6699 } 6725 6700 6726 - static int ci_dpm_get_mclk_od(struct amdgpu_device *adev) 6701 + static int ci_dpm_get_mclk_od(void *handle) 6727 6702 { 6703 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6728 6704 struct ci_power_info *pi = ci_get_pi(adev); 6729 6705 struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table); 6730 6706 struct ci_single_dpm_table *golden_mclk_table = ··· 6740 6714 return value; 6741 6715 } 6742 6716 6743 - static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 6717 + static int ci_dpm_set_mclk_od(void *handle, uint32_t value) 6744 6718 { 6719 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6745 6720 struct ci_power_info *pi = ci_get_pi(adev); 6746 6721 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps); 6747 6722 struct ci_single_dpm_table *golden_mclk_table = ··· 6759 6732 return 0; 6760 6733 } 6761 6734 6762 - static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev, 6735 + static int ci_dpm_get_power_profile_state(void *handle, 6763 6736 struct amd_pp_profile *query) 6764 6737 { 6738 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6765 6739 struct ci_power_info *pi = ci_get_pi(adev); 6766 6740 6767 6741 if (!pi || !query) ··· 6879 6851 return result; 6880 6852 } 6881 6853 6882 - static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev, 6854 + static int ci_dpm_set_power_profile_state(void *handle, 6883 6855 struct amd_pp_profile *request) 6884 6856 { 6857 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6885 6858 struct ci_power_info *pi = ci_get_pi(adev); 6886 6859 int ret = -1; 6887 6860 ··· 6935 6906 return 0; 6936 6907 } 6937 6908 6938 - static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev, 6909 + static int ci_dpm_reset_power_profile_state(void *handle, 6939 6910 struct amd_pp_profile *request) 6940 6911 { 6912 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6941 6913 struct ci_power_info *pi = ci_get_pi(adev); 6942 6914 6943 6915 if (!pi || !request) ··· 6957 6927 return -EINVAL; 6958 6928 } 6959 6929 6960 - static int ci_dpm_switch_power_profile(struct amdgpu_device *adev, 6930 + static int ci_dpm_switch_power_profile(void *handle, 6961 6931 enum amd_pp_profile_type type) 6962 6932 { 6933 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6963 6934 struct ci_power_info *pi = ci_get_pi(adev); 6964 6935 struct amd_pp_profile request = {0}; 6965 6936 ··· 6975 6944 return 0; 6976 6945 } 6977 6946 6978 - static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx, 6947 + static int ci_dpm_read_sensor(void *handle, int idx, 6979 6948 void *value, int *size) 6980 6949 { 6981 6950 u32 activity_percent = 50; 6982 6951 int ret; 6952 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6983 6953 6984 6954 /* size must be at least 4 bytes for all sensors */ 6985 6955 if (*size < 4) ··· 7035 7003 .set_powergating_state = ci_dpm_set_powergating_state, 7036 7004 }; 7037 7005 7038 - static const struct amdgpu_dpm_funcs ci_dpm_funcs = { 7006 + static const struct amd_pm_funcs ci_dpm_funcs = { 7039 7007 .get_temperature = &ci_dpm_get_temp, 7040 7008 .pre_set_power_state = &ci_dpm_pre_set_power_state, 7041 7009 .set_power_state = &ci_dpm_set_power_state,
+34 -19
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
··· 64 64 int min_temp, int max_temp); 65 65 static int kv_init_fps_limits(struct amdgpu_device *adev); 66 66 67 - static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); 67 + static void kv_dpm_powergate_uvd(void *handle, bool gate); 68 68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate); 69 69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); 70 70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); ··· 1245 1245 adev->pm.dpm.requested_ps = &pi->requested_rps; 1246 1246 } 1247 1247 1248 - static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable) 1248 + static void kv_dpm_enable_bapm(void *handle, bool enable) 1249 1249 { 1250 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 struct kv_power_info *pi = kv_get_pi(adev); 1251 1252 int ret; 1252 1253 ··· 1673 1672 return kv_enable_acp_dpm(adev, !gate); 1674 1673 } 1675 1674 1676 - static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) 1675 + static void kv_dpm_powergate_uvd(void *handle, bool gate) 1677 1676 { 1677 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1678 1678 struct kv_power_info *pi = kv_get_pi(adev); 1679 1679 int ret; 1680 1680 ··· 1870 1868 return ret; 1871 1869 } 1872 1870 1873 - static int kv_dpm_force_performance_level(struct amdgpu_device *adev, 1871 + static int kv_dpm_force_performance_level(void *handle, 1874 1872 enum amd_dpm_forced_level level) 1875 1873 { 1876 1874 int ret; 1875 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1877 1876 1878 1877 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 1879 1878 ret = kv_force_dpm_highest(adev); ··· 1895 1892 return 0; 1896 1893 } 1897 1894 1898 - static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev) 1895 + static int kv_dpm_pre_set_power_state(void *handle) 1899 1896 { 1897 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1900 1898 struct kv_power_info *pi = kv_get_pi(adev); 1901 1899 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 1902 1900 struct amdgpu_ps *new_ps = &requested_ps; ··· 1911 1907 return 0; 1912 1908 } 1913 1909 1914 - static int kv_dpm_set_power_state(struct amdgpu_device *adev) 1910 + static int kv_dpm_set_power_state(void *handle) 1915 1911 { 1912 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1916 1913 struct kv_power_info *pi = kv_get_pi(adev); 1917 1914 struct amdgpu_ps *new_ps = &pi->requested_rps; 1918 1915 struct amdgpu_ps *old_ps = &pi->current_rps; ··· 1986 1981 return 0; 1987 1982 } 1988 1983 1989 - static void kv_dpm_post_set_power_state(struct amdgpu_device *adev) 1984 + static void kv_dpm_post_set_power_state(void *handle) 1990 1985 { 1986 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1991 1987 struct kv_power_info *pi = kv_get_pi(adev); 1992 1988 struct amdgpu_ps *new_ps = &pi->requested_rps; 1993 1989 ··· 2854 2848 } 2855 2849 2856 2850 static void 2857 - kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 2851 + kv_dpm_debugfs_print_current_performance_level(void *handle, 2858 2852 struct seq_file *m) 2859 2853 { 2854 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2860 2855 struct kv_power_info *pi = kv_get_pi(adev); 2861 2856 u32 current_index = 2862 2857 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & ··· 2882 2875 } 2883 2876 2884 2877 static void 2885 - kv_dpm_print_power_state(struct amdgpu_device *adev, 2886 - struct amdgpu_ps *rps) 2878 + kv_dpm_print_power_state(void *handle, void *request_ps) 2887 2879 { 2888 2880 int i; 2881 + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 2889 2882 struct kv_ps *ps = kv_get_ps(rps); 2883 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2890 2884 2891 2885 amdgpu_dpm_print_class_info(rps->class, rps->class2); 2892 2886 amdgpu_dpm_print_cap_info(rps->caps); ··· 2913 2905 amdgpu_free_extended_power_table(adev); 2914 2906 } 2915 2907 2916 - static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev) 2908 + static void kv_dpm_display_configuration_changed(void *handle) 2917 2909 { 2918 2910 2919 2911 } 2920 2912 2921 - static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low) 2913 + static u32 kv_dpm_get_sclk(void *handle, bool low) 2922 2914 { 2915 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2923 2916 struct kv_power_info *pi = kv_get_pi(adev); 2924 2917 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2925 2918 ··· 2930 2921 return requested_state->levels[requested_state->num_levels - 1].sclk; 2931 2922 } 2932 2923 2933 - static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low) 2924 + static u32 kv_dpm_get_mclk(void *handle, bool low) 2934 2925 { 2926 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2935 2927 struct kv_power_info *pi = kv_get_pi(adev); 2936 2928 2937 2929 return pi->sys_info.bootup_uma_clk; 2938 2930 } 2939 2931 2940 2932 /* get temperature in millidegrees */ 2941 - static int kv_dpm_get_temp(struct amdgpu_device *adev) 2933 + static int kv_dpm_get_temp(void *handle) 2942 2934 { 2943 2935 u32 temp; 2944 2936 int actual_temp = 0; 2937 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2945 2938 2946 2939 temp = RREG32_SMC(0xC0300E0C); 2947 2940 ··· 3233 3222 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state)); 3234 3223 } 3235 3224 3236 - static int kv_check_state_equal(struct amdgpu_device *adev, 3237 - struct amdgpu_ps *cps, 3238 - struct amdgpu_ps *rps, 3225 + static int kv_check_state_equal(void *handle, 3226 + void *current_ps, 3227 + void *request_ps, 3239 3228 bool *equal) 3240 3229 { 3241 3230 struct kv_ps *kv_cps; 3242 3231 struct kv_ps *kv_rps; 3243 3232 int i; 3233 + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 3234 + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 3235 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3244 3236 3245 3237 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 3246 3238 return -EINVAL; ··· 3276 3262 return 0; 3277 3263 } 3278 3264 3279 - static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx, 3265 + static int kv_dpm_read_sensor(void *handle, int idx, 3280 3266 void *value, int *size) 3281 3267 { 3268 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3282 3269 struct kv_power_info *pi = kv_get_pi(adev); 3283 3270 uint32_t sclk; 3284 3271 u32 pl_index = ··· 3327 3312 .set_powergating_state = kv_dpm_set_powergating_state, 3328 3313 }; 3329 3314 3330 - static const struct amdgpu_dpm_funcs kv_dpm_funcs = { 3315 + static const struct amd_pm_funcs kv_dpm_funcs = { 3331 3316 .get_temperature = &kv_dpm_get_temp, 3332 3317 .pre_set_power_state = &kv_dpm_pre_set_power_state, 3333 3318 .set_power_state = &kv_dpm_set_power_state,
+45 -24
drivers/gpu/drm/amd/amdgpu/si_dpm.c
··· 3060 3060 return ret; 3061 3061 } 3062 3062 3063 - static bool si_dpm_vblank_too_short(struct amdgpu_device *adev) 3063 + static bool si_dpm_vblank_too_short(void *handle) 3064 3064 { 3065 - 3065 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3066 3066 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3067 3067 /* we never hit the non-gddr5 limit so disable it */ 3068 3068 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; ··· 3871 3871 0 : -EINVAL; 3872 3872 } 3873 3873 3874 - static int si_dpm_force_performance_level(struct amdgpu_device *adev, 3874 + static int si_dpm_force_performance_level(void *handle, 3875 3875 enum amd_dpm_forced_level level) 3876 3876 { 3877 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3877 3878 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3878 3879 struct si_ps *ps = si_get_ps(rps); 3879 3880 u32 levels = ps->performance_level_count; ··· 6576 6575 } 6577 6576 } 6578 6577 6579 - static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev, 6578 + static int si_dpm_get_fan_speed_percent(void *handle, 6580 6579 u32 *speed) 6581 6580 { 6582 6581 u32 duty, duty100; 6583 6582 u64 tmp64; 6583 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6584 6584 6585 6585 if (adev->pm.no_fan) 6586 6586 return -ENOENT; ··· 6602 6600 return 0; 6603 6601 } 6604 6602 6605 - static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev, 6603 + static int si_dpm_set_fan_speed_percent(void *handle, 6606 6604 u32 speed) 6607 6605 { 6606 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6608 6607 struct si_power_info *si_pi = si_get_pi(adev); 6609 6608 u32 tmp; 6610 6609 u32 duty, duty100; ··· 6636 6633 return 0; 6637 6634 } 6638 6635 6639 - static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) 6636 + static void si_dpm_set_fan_control_mode(void *handle, u32 mode) 6640 6637 { 6638 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6639 + 6641 6640 if (mode) { 6642 6641 /* stop auto-manage */ 6643 6642 if (adev->pm.dpm.fan.ucode_fan_control) ··· 6654 6649 } 6655 6650 } 6656 6651 6657 - static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev) 6652 + static u32 si_dpm_get_fan_control_mode(void *handle) 6658 6653 { 6654 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6659 6655 struct si_power_info *si_pi = si_get_pi(adev); 6660 6656 u32 tmp; 6661 6657 ··· 6952 6946 ni_update_current_ps(adev, boot_ps); 6953 6947 } 6954 6948 6955 - static int si_dpm_pre_set_power_state(struct amdgpu_device *adev) 6949 + static int si_dpm_pre_set_power_state(void *handle) 6956 6950 { 6951 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6957 6952 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6958 6953 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 6959 6954 struct amdgpu_ps *new_ps = &requested_ps; ··· 6991 6984 return 0; 6992 6985 } 6993 6986 6994 - static int si_dpm_set_power_state(struct amdgpu_device *adev) 6987 + static int si_dpm_set_power_state(void *handle) 6995 6988 { 6989 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6996 6990 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6997 6991 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 6998 6992 struct amdgpu_ps *old_ps = &eg_pi->current_rps; ··· 7094 7086 return 0; 7095 7087 } 7096 7088 7097 - static void si_dpm_post_set_power_state(struct amdgpu_device *adev) 7089 + static void si_dpm_post_set_power_state(void *handle) 7098 7090 { 7091 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7099 7092 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7100 7093 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7101 7094 ··· 7112 7103 } 7113 7104 #endif 7114 7105 7115 - static void si_dpm_display_configuration_changed(struct amdgpu_device *adev) 7106 + static void si_dpm_display_configuration_changed(void *handle) 7116 7107 { 7108 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7109 + 7117 7110 si_program_display_gap(adev); 7118 7111 } 7119 7112 ··· 7497 7486 amdgpu_free_extended_power_table(adev); 7498 7487 } 7499 7488 7500 - static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 7489 + static void si_dpm_debugfs_print_current_performance_level(void *handle, 7501 7490 struct seq_file *m) 7502 7491 { 7492 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7503 7493 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7504 7494 struct amdgpu_ps *rps = &eg_pi->current_rps; 7505 7495 struct si_ps *ps = si_get_ps(rps); ··· 7872 7860 } 7873 7861 7874 7862 /* get temperature in millidegrees */ 7875 - static int si_dpm_get_temp(struct amdgpu_device *adev) 7863 + static int si_dpm_get_temp(void *handle) 7876 7864 { 7877 7865 u32 temp; 7878 7866 int actual_temp = 0; 7867 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7879 7868 7880 7869 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 7881 7870 CTF_TEMP_SHIFT; ··· 7891 7878 return actual_temp; 7892 7879 } 7893 7880 7894 - static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low) 7881 + static u32 si_dpm_get_sclk(void *handle, bool low) 7895 7882 { 7883 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7896 7884 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7897 7885 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7898 7886 ··· 7903 7889 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7904 7890 } 7905 7891 7906 - static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low) 7892 + static u32 si_dpm_get_mclk(void *handle, bool low) 7907 7893 { 7894 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7908 7895 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7909 7896 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7910 7897 ··· 7915 7900 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7916 7901 } 7917 7902 7918 - static void si_dpm_print_power_state(struct amdgpu_device *adev, 7919 - struct amdgpu_ps *rps) 7903 + static void si_dpm_print_power_state(void *handle, 7904 + void *current_ps) 7920 7905 { 7906 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7907 + struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7921 7908 struct si_ps *ps = si_get_ps(rps); 7922 7909 struct rv7xx_pl *pl; 7923 7910 int i; ··· 7959 7942 (si_cpl1->vddci == si_cpl2->vddci)); 7960 7943 } 7961 7944 7962 - static int si_check_state_equal(struct amdgpu_device *adev, 7963 - struct amdgpu_ps *cps, 7964 - struct amdgpu_ps *rps, 7945 + static int si_check_state_equal(void *handle, 7946 + void *current_ps, 7947 + void *request_ps, 7965 7948 bool *equal) 7966 7949 { 7967 7950 struct si_ps *si_cps; 7968 7951 struct si_ps *si_rps; 7969 7952 int i; 7953 + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 7954 + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 7955 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7970 7956 7971 7957 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 7972 7958 return -EINVAL; 7973 7959 7974 - si_cps = si_get_ps(cps); 7975 - si_rps = si_get_ps(rps); 7960 + si_cps = si_get_ps((struct amdgpu_ps *)cps); 7961 + si_rps = si_get_ps((struct amdgpu_ps *)rps); 7976 7962 7977 7963 if (si_cps == NULL) { 7978 7964 printk("si_cps is NULL\n"); ··· 8003 7983 return 0; 8004 7984 } 8005 7985 8006 - static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx, 7986 + static int si_dpm_read_sensor(void *handle, int idx, 8007 7987 void *value, int *size) 8008 7988 { 7989 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8009 7990 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8010 7991 struct amdgpu_ps *rps = &eg_pi->current_rps; 8011 7992 struct si_ps *ps = si_get_ps(rps); ··· 8062 8041 .set_powergating_state = si_dpm_set_powergating_state, 8063 8042 }; 8064 8043 8065 - static const struct amdgpu_dpm_funcs si_dpm_funcs = { 8044 + static const struct amd_pm_funcs si_dpm_funcs = { 8066 8045 .get_temperature = &si_dpm_get_temp, 8067 8046 .pre_set_power_state = &si_dpm_pre_set_power_state, 8068 8047 .set_power_state = &si_dpm_set_power_state,
+51
drivers/gpu/drm/amd/include/amd_shared.h
··· 25 25 26 26 #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 27 27 28 + struct seq_file; 29 + 28 30 /* 29 31 * Supported ASIC types 30 32 */ ··· 146 144 AMD_FAN_CTRL_AUTO = 2, 147 145 }; 148 146 147 + enum pp_clock_type { 148 + PP_SCLK, 149 + PP_MCLK, 150 + PP_PCIE, 151 + }; 152 + 149 153 /* CG flags */ 150 154 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 151 155 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) ··· 255 247 enum amd_powergating_state state); 256 248 /* get current clockgating status */ 257 249 void (*get_clockgating_state)(void *handle, u32 *flags); 250 + }; 251 + 252 + struct amd_pm_funcs { 253 + int (*get_temperature)(void *handle); 254 + int (*pre_set_power_state)(void *handle); 255 + int (*set_power_state)(void *handle); 256 + void (*post_set_power_state)(void *handle); 257 + void (*display_configuration_changed)(void *handle); 258 + u32 (*get_sclk)(void *handle, bool low); 259 + u32 (*get_mclk)(void *handle, bool low); 260 + void (*print_power_state)(void *handle, void *ps); 261 + void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 262 + int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 263 + bool (*vblank_too_short)(void *handle); 264 + void (*powergate_uvd)(void *handle, bool gate); 265 + void (*powergate_vce)(void *handle, bool gate); 266 + void (*enable_bapm)(void *handle, bool enable); 267 + void (*set_fan_control_mode)(void *handle, u32 mode); 268 + u32 (*get_fan_control_mode)(void *handle); 269 + int (*set_fan_speed_percent)(void *handle, u32 speed); 270 + int (*get_fan_speed_percent)(void *handle, u32 *speed); 271 + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 272 + int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 273 + int (*get_sclk_od)(void *handle); 274 + int (*set_sclk_od)(void *handle, uint32_t value); 275 + int (*get_mclk_od)(void *handle); 276 + int (*set_mclk_od)(void *handle, uint32_t value); 277 + int (*check_state_equal)(void *handle, 278 + void *cps, 279 + void *rps, 280 + bool *equal); 281 + int (*read_sensor)(void *handle, int idx, void *value, 282 + int *size); 283 + 284 + struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); 285 + int (*reset_power_profile_state)(void *handle, 286 + struct amd_pp_profile *request); 287 + int (*get_power_profile_state)(void *handle, 288 + struct amd_pp_profile *query); 289 + int (*set_power_profile_state)(void *handle, 290 + struct amd_pp_profile *request); 291 + int (*switch_power_profile)(void *handle, 292 + enum amd_pp_profile_type type); 258 293 }; 259 294 260 295 #endif /* __AMD_SHARED_H__ */
-6
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
··· 213 213 PP_GROUP_MAX 214 214 }; 215 215 216 - enum pp_clock_type { 217 - PP_SCLK, 218 - PP_MCLK, 219 - PP_PCIE, 220 - }; 221 - 222 216 struct pp_states_info { 223 217 uint32_t nums; 224 218 uint32_t states[16];