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kernel os linux

drm/amd/powerplay: delete dead code in powerplay

delete functiontable related codes

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
698f88e6 cf2623d9

+22 -310
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
··· 2 2 # Makefile for the 'hw manager' sub-component of powerplay. 3 3 # It provides the hardware management services for the driver. 4 4 5 - HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ 5 + HARDWARE_MGR = hwmgr.o processpptables.o \ 6 6 hardwaremanager.o pp_acpi.o cz_hwmgr.o \ 7 7 cz_clockpowergating.o pppcielanes.o\ 8 8 process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
+1 -2
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
··· 1142 1142 return -ENOMEM; 1143 1143 1144 1144 hwmgr->backend = data; 1145 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1146 - PHM_PlatformCaps_TablelessHardwareInterface); 1145 + 1147 1146 result = cz_initialize_dpm_defaults(hwmgr); 1148 1147 if (result != 0) { 1149 1148 pr_err("cz_initialize_dpm_defaults failed\n");
-161
drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
··· 1 - /* 2 - * Copyright 2015 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included in 12 - * all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 - * OTHER DEALINGS IN THE SOFTWARE. 21 - * 22 - */ 23 - #include <linux/types.h> 24 - #include <linux/kernel.h> 25 - #include <linux/slab.h> 26 - #include "hwmgr.h" 27 - 28 - static int phm_run_table(struct pp_hwmgr *hwmgr, 29 - struct phm_runtime_table_header *rt_table, 30 - void *input, 31 - void *output, 32 - void *temp_storage) 33 - { 34 - int result = 0; 35 - phm_table_function *function; 36 - 37 - if (rt_table->function_list == NULL) { 38 - pr_debug("this function not implement!\n"); 39 - return 0; 40 - } 41 - 42 - for (function = rt_table->function_list; NULL != *function; function++) { 43 - int tmp = (*function)(hwmgr, input, output, temp_storage, result); 44 - 45 - if (tmp == PP_Result_TableImmediateExit) 46 - break; 47 - if (tmp) { 48 - if (0 == result) 49 - result = tmp; 50 - if (rt_table->exit_error) 51 - break; 52 - } 53 - } 54 - 55 - return result; 56 - } 57 - 58 - int phm_dispatch_table(struct pp_hwmgr *hwmgr, 59 - struct phm_runtime_table_header *rt_table, 60 - void *input, void *output) 61 - { 62 - int result; 63 - void *temp_storage; 64 - 65 - if (hwmgr == NULL || rt_table == NULL) { 66 - pr_err("Invalid Parameter!\n"); 67 - return -EINVAL; 68 - } 69 - 70 - if (0 != rt_table->storage_size) { 71 - temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL); 72 - if (temp_storage == NULL) { 73 - pr_err("Could not allocate table temporary storage\n"); 74 - return -ENOMEM; 75 - } 76 - } else { 77 - temp_storage = NULL; 78 - } 79 - 80 - result = phm_run_table(hwmgr, rt_table, input, output, temp_storage); 81 - 82 - kfree(temp_storage); 83 - 84 - return result; 85 - } 86 - 87 - int phm_construct_table(struct pp_hwmgr *hwmgr, 88 - const struct phm_master_table_header *master_table, 89 - struct phm_runtime_table_header *rt_table) 90 - { 91 - uint32_t function_count = 0; 92 - const struct phm_master_table_item *table_item; 93 - uint32_t size; 94 - phm_table_function *run_time_list; 95 - phm_table_function *rtf; 96 - 97 - if (hwmgr == NULL || master_table == NULL || rt_table == NULL) { 98 - pr_err("Invalid Parameter!\n"); 99 - return -EINVAL; 100 - } 101 - 102 - for (table_item = master_table->master_list; 103 - NULL != table_item->tableFunction; table_item++) { 104 - if ((NULL == table_item->isFunctionNeededInRuntimeTable) || 105 - (table_item->isFunctionNeededInRuntimeTable(hwmgr))) 106 - function_count++; 107 - } 108 - 109 - size = (function_count + 1) * sizeof(phm_table_function); 110 - run_time_list = kzalloc(size, GFP_KERNEL); 111 - 112 - if (NULL == run_time_list) 113 - return -ENOMEM; 114 - 115 - rtf = run_time_list; 116 - for (table_item = master_table->master_list; 117 - NULL != table_item->tableFunction; table_item++) { 118 - if ((rtf - run_time_list) > function_count) { 119 - pr_err("Check function results have changed\n"); 120 - kfree(run_time_list); 121 - return -EINVAL; 122 - } 123 - 124 - if ((NULL == table_item->isFunctionNeededInRuntimeTable) || 125 - (table_item->isFunctionNeededInRuntimeTable(hwmgr))) { 126 - *(rtf++) = table_item->tableFunction; 127 - } 128 - } 129 - 130 - if ((rtf - run_time_list) > function_count) { 131 - pr_err("Check function results have changed\n"); 132 - kfree(run_time_list); 133 - return -EINVAL; 134 - } 135 - 136 - *rtf = NULL; 137 - rt_table->function_list = run_time_list; 138 - rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError)); 139 - rt_table->storage_size = master_table->storage_size; 140 - return 0; 141 - } 142 - 143 - int phm_destroy_table(struct pp_hwmgr *hwmgr, 144 - struct phm_runtime_table_header *rt_table) 145 - { 146 - if (hwmgr == NULL || rt_table == NULL) { 147 - pr_err("Invalid Parameter\n"); 148 - return -EINVAL; 149 - } 150 - 151 - if (NULL == rt_table->function_list) 152 - return 0; 153 - 154 - kfree(rt_table->function_list); 155 - 156 - rt_table->function_list = NULL; 157 - rt_table->storage_size = 0; 158 - rt_table->exit_error = false; 159 - 160 - return 0; 161 - }
+20 -73
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
··· 36 36 return -EINVAL; \ 37 37 } while (0) 38 38 39 - bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr) 40 - { 41 - return hwmgr->block_hw_access; 42 - } 43 - 44 - int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block) 45 - { 46 - hwmgr->block_hw_access = block; 47 - return 0; 48 - } 49 - 50 39 int phm_setup_asic(struct pp_hwmgr *hwmgr) 51 40 { 52 41 PHM_FUNC_CHECK(hwmgr); 53 42 54 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 55 - PHM_PlatformCaps_TablelessHardwareInterface)) { 56 - if (NULL != hwmgr->hwmgr_func->asic_setup) 57 - return hwmgr->hwmgr_func->asic_setup(hwmgr); 58 - } else { 59 - return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic), 60 - NULL, NULL); 61 - } 43 + if (NULL != hwmgr->hwmgr_func->asic_setup) 44 + return hwmgr->hwmgr_func->asic_setup(hwmgr); 62 45 63 46 return 0; 64 47 } ··· 50 67 { 51 68 PHM_FUNC_CHECK(hwmgr); 52 69 53 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 54 - PHM_PlatformCaps_TablelessHardwareInterface)) { 55 - if (NULL != hwmgr->hwmgr_func->power_off_asic) 56 - return hwmgr->hwmgr_func->power_off_asic(hwmgr); 57 - } else { 58 - return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic), 59 - NULL, NULL); 60 - } 70 + if (NULL != hwmgr->hwmgr_func->power_off_asic) 71 + return hwmgr->hwmgr_func->power_off_asic(hwmgr); 61 72 62 73 return 0; 63 74 } ··· 67 90 states.pcurrent_state = pcurrent_state; 68 91 states.pnew_state = pnew_power_state; 69 92 70 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 71 - PHM_PlatformCaps_TablelessHardwareInterface)) { 72 - if (NULL != hwmgr->hwmgr_func->power_state_set) 73 - return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); 74 - } else { 75 - return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL); 76 - } 93 + if (NULL != hwmgr->hwmgr_func->power_state_set) 94 + return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); 77 95 78 96 return 0; 79 97 } ··· 79 107 bool enabled; 80 108 PHM_FUNC_CHECK(hwmgr); 81 109 82 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 83 - PHM_PlatformCaps_TablelessHardwareInterface)) { 84 - if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 85 - ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 86 - } else { 87 - ret = phm_dispatch_table(hwmgr, 88 - &(hwmgr->enable_dynamic_state_management), 89 - NULL, NULL); 90 - } 110 + if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 111 + ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 91 112 92 113 enabled = ret == 0; 93 114 ··· 96 131 97 132 PHM_FUNC_CHECK(hwmgr); 98 133 99 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 100 - PHM_PlatformCaps_TablelessHardwareInterface)) { 101 - if (hwmgr->hwmgr_func->dynamic_state_management_disable) 102 - ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); 103 - } else { 104 - ret = phm_dispatch_table(hwmgr, 105 - &(hwmgr->disable_dynamic_state_management), 106 - NULL, NULL); 107 - } 134 + if (hwmgr->hwmgr_func->dynamic_state_management_disable) 135 + ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); 108 136 109 137 enabled = ret == 0 ? false : true; 110 138 ··· 177 219 { 178 220 PHM_FUNC_CHECK(hwmgr); 179 221 180 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 181 - PHM_PlatformCaps_TablelessHardwareInterface)) { 182 - if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) 183 - return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); 184 - } else { 185 - return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL); 186 - } 222 + if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) 223 + return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); 224 + 187 225 return 0; 188 226 } 189 227 ··· 187 233 { 188 234 PHM_FUNC_CHECK(hwmgr); 189 235 190 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 191 - PHM_PlatformCaps_TablelessHardwareInterface)) { 192 - if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) 193 - return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); 194 - } 236 + if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) 237 + return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); 238 + 195 239 return 0; 196 240 } 197 241 ··· 198 246 { 199 247 PHM_FUNC_CHECK(hwmgr); 200 248 201 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 202 - PHM_PlatformCaps_TablelessHardwareInterface)) { 203 - if (NULL != hwmgr->hwmgr_func->display_config_changed) 204 - hwmgr->hwmgr_func->display_config_changed(hwmgr); 205 - } else 206 - return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL); 249 + if (NULL != hwmgr->hwmgr_func->display_config_changed) 250 + hwmgr->hwmgr_func->display_config_changed(hwmgr); 251 + 207 252 return 0; 208 253 } 209 254 ··· 208 259 { 209 260 PHM_FUNC_CHECK(hwmgr); 210 261 211 - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 212 - PHM_PlatformCaps_TablelessHardwareInterface)) 213 - if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) 262 + if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) 214 263 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); 215 264 216 265 return 0;
-12
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 852 852 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 853 853 PHM_PlatformCaps_AutomaticDCTransition); 854 854 855 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 856 - PHM_PlatformCaps_TablelessHardwareInterface); 857 - 858 - 859 855 if (hwmgr->chip_id != CHIP_POLARIS10) 860 856 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 861 857 PHM_PlatformCaps_SPLLShutdownSupport); ··· 878 882 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 879 883 PHM_PlatformCaps_TCPRamping); 880 884 881 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 882 - PHM_PlatformCaps_TablelessHardwareInterface); 883 - 884 885 return 0; 885 886 } 886 887 ··· 897 904 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 898 905 PHM_PlatformCaps_VCEPowerGating); 899 906 900 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 901 - PHM_PlatformCaps_TablelessHardwareInterface); 902 - 903 907 return 0; 904 908 } 905 909 ··· 910 920 PHM_PlatformCaps_TDRamping); 911 921 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 912 922 PHM_PlatformCaps_TCPRamping); 913 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 914 - PHM_PlatformCaps_TablelessHardwareInterface); 915 923 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 916 924 PHM_PlatformCaps_EVV); 917 925 return 0;
-3
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
··· 435 435 436 436 hwmgr->backend = data; 437 437 438 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 439 - PHM_PlatformCaps_TablelessHardwareInterface); 440 - 441 438 result = rv_initialize_dpm_defaults(hwmgr); 442 439 if (result != 0) { 443 440 pr_err("rv_initialize_dpm_defaults failed\n");
-6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 3854 3854 hwmgr->thermal_controller. 3855 3855 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 3856 3856 3857 - if (phm_is_hw_access_blocked(hwmgr)) 3858 - return 0; 3859 - 3860 3857 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3861 3858 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); 3862 3859 } ··· 3955 3958 { 3956 3959 hwmgr->thermal_controller. 3957 3960 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 3958 - 3959 - if (phm_is_hw_access_blocked(hwmgr)) 3960 - return 0; 3961 3961 3962 3962 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3963 3963 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
-3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 201 201 PHM_PlatformCaps_ControlVDDCI); 202 202 203 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 - PHM_PlatformCaps_TablelessHardwareInterface); 205 - 206 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 207 204 PHM_PlatformCaps_EnableSMU7ThermalManagement); 208 205 209 206 sys_info.size = sizeof(struct cgs_system_info);
-49
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
··· 109 109 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 110 110 #define PHM_PCIE_POWERGATING_TARGET_PHY 3 111 111 112 - typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, 113 - void *output, void *storage, int result); 114 - 115 - typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); 116 112 117 113 struct phm_set_power_state_input { 118 114 const struct pp_hw_power_state *pcurrent_state; ··· 143 147 uint32_t num_cus; 144 148 uint32_t gfxclk; 145 149 uint32_t fclk; 146 - }; 147 - 148 - /* Entries in the master tables */ 149 - struct phm_master_table_item { 150 - phm_check_function isFunctionNeededInRuntimeTable; 151 - phm_table_function tableFunction; 152 - }; 153 - 154 - enum phm_master_table_flag { 155 - PHM_MasterTableFlag_None = 0, 156 - PHM_MasterTableFlag_ExitOnError = 1, 157 - }; 158 - 159 - /* The header of the master tables */ 160 - struct phm_master_table_header { 161 - uint32_t storage_size; 162 - uint32_t flags; 163 - const struct phm_master_table_item *master_list; 164 - }; 165 - 166 - struct phm_runtime_table_header { 167 - uint32_t storage_size; 168 - bool exit_error; 169 - phm_table_function *function_list; 170 150 }; 171 151 172 152 struct phm_clock_array { ··· 187 215 uint32_t Sclk; 188 216 uint32_t Mclk; 189 217 }; 190 - 191 - 192 - extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, 193 - struct phm_runtime_table_header *rt_table, 194 - void *input, void *output); 195 - 196 - extern int phm_construct_table(struct pp_hwmgr *hwmgr, 197 - const struct phm_master_table_header *master_table, 198 - struct phm_runtime_table_header *rt_table); 199 - 200 - extern int phm_destroy_table(struct pp_hwmgr *hwmgr, 201 - struct phm_runtime_table_header *rt_table); 202 - 203 218 204 219 struct phm_uvd_clock_voltage_dependency_record { 205 220 uint32_t vclk; ··· 708 749 enum amd_dpm_forced_level dpm_level; 709 750 enum amd_dpm_forced_level saved_dpm_level; 710 751 enum amd_dpm_forced_level request_dpm_level; 711 - bool block_hw_access; 712 752 struct phm_gfx_arbiter gfx_arbiter; 713 753 struct phm_acp_arbiter acp_arbiter; 714 754 struct phm_uvd_arbiter uvd_arbiter; ··· 718 760 void *backend; 719 761 enum PP_DAL_POWERLEVEL dal_power_level; 720 762 struct phm_dynamic_state_info dyn_state; 721 - struct phm_runtime_table_header setup_asic; 722 - struct phm_runtime_table_header power_down_asic; 723 - struct phm_runtime_table_header disable_dynamic_state_management; 724 - struct phm_runtime_table_header enable_dynamic_state_management; 725 - struct phm_runtime_table_header set_power_state; 726 - struct phm_runtime_table_header enable_clock_power_gatings; 727 - struct phm_runtime_table_header display_configuration_changed; 728 763 const struct pp_hwmgr_func *hwmgr_func; 729 764 const struct pp_table_func *pptable_func; 730 765 struct pp_power_state *ps;