net: pcs: xpcs: add _modify() accessors

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The xpcs driver does a lot of read-modify-write operations on
registers, which leads to long-winded code to read the register, check
whether the read was successful, modify the value in some way, and then
write it back.

We have a mdiodev _modify() accessor that encapsulates this, and does
the register modification under the MDIO bus lock ensuring that the
modification is atomic with respect to other bus operations. Convert
the xpcs driver to use this accessor.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Russell King (Oracle) and committed by

David S. Miller 2 years ago ce8d6081 f6818918

+108 -146

4 changed files

expand all

drivers

net

pcs

pcs-xpcs-nxp.c

pcs-xpcs-wx.c

pcs-xpcs.c

pcs-xpcs.h

+8 -16

drivers/net/pcs/pcs-xpcs-nxp.c

··· 152 152 /* Enable TX and RX PLLs and circuits. 153 153 * Release reset of PMA to enable data flow to/from PCS. 154 154 */ 155 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE); 156 - if (ret < 0) 157 - return ret; 158 - 159 - val = ret & ~(SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD | 160 - SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN | 161 - SJA1110_RESET_SER | SJA1110_RESET_DES); 162 - val |= SJA1110_RXPKDETEN | SJA1110_RCVEN; 163 - 164 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, val); 155 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, 156 + SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD | 157 + SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN | 158 + SJA1110_RESET_SER | SJA1110_RESET_DES | 159 + SJA1110_RXPKDETEN | SJA1110_RCVEN, 160 + SJA1110_RXPKDETEN | SJA1110_RCVEN); 165 161 if (ret < 0) 166 162 return ret; 167 163 168 164 /* Program continuous-time linear equalizer (CTLE) settings. */ 169 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE, 170 - rx_cdr_ctle); 171 - if (ret < 0) 172 - return ret; 173 - 174 - return 0; 165 + return xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE, 166 + rx_cdr_ctle); 175 167 } 176 168 177 169 int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs)

+23 -35

drivers/net/pcs/pcs-xpcs-wx.c

··· 46 46 #define TXGBE_VCO_CAL_LD0 0x72 47 47 #define TXGBE_VCO_CAL_REF0 0x76 48 48 49 - static int txgbe_read_pma(struct dw_xpcs *xpcs, int reg) 50 - { 51 - return xpcs_read(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg); 52 - } 53 - 54 49 static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val) 55 50 { 56 51 return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val); 57 52 } 58 53 54 + static int txgbe_modify_pma(struct dw_xpcs *xpcs, int reg, u16 mask, u16 set) 55 + { 56 + return xpcs_modify(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, mask, 57 + set); 58 + } 59 + 59 60 static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs) 60 61 { 61 - int val; 62 - 63 62 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21); 64 63 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0); 65 - val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1); 66 - val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL); 67 - txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val); 64 + txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, TXGBE_TX_GENCTL1_VBOOST_LVL, 65 + FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5)); 68 66 txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL | 69 67 TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF)); 70 68 txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549); ··· 76 78 77 79 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) | 78 80 TXGBE_RX_EQ_CTL0_CTLE_BOOST(5)); 79 - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL); 80 - val &= ~TXGBE_RX_EQ_ATTN_LVL0; 81 - txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val); 81 + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0); 82 82 txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE); 83 - val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE); 84 - val &= ~(TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0); 85 - txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val); 86 - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4); 87 - val &= ~TXGBE_RX_EQ_CTL4_CONT_ADAPT0; 88 - txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val); 83 + txgbe_modify_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 84 + TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0, 0); 85 + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_ADAPT0, 86 + 0); 89 87 } 90 88 91 89 static void txgbe_pma_config_1g(struct dw_xpcs *xpcs) 92 90 { 93 - int val; 94 - 95 - val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1); 96 - val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL); 97 - val &= ~TXGBE_TX_GENCTL1_VBOOST_EN0; 98 - txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val); 91 + txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, 92 + TXGBE_TX_GENCTL1_VBOOST_LVL | 93 + TXGBE_TX_GENCTL1_VBOOST_EN0, 94 + FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5)); 99 95 txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL | 100 96 TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF)); 101 97 102 98 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) | 103 99 TXGBE_RX_EQ_CTL0_VGA2_GAIN(7) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(6)); 104 - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL); 105 - val &= ~TXGBE_RX_EQ_ATTN_LVL0; 106 - txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val); 100 + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0); 107 101 txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0); 108 - val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3); 109 - val = u16_replace_bits(val, 0x4, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0); 110 - txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL3, val); 102 + txgbe_modify_pma(xpcs, TXGBE_RX_GEN_CTL3, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0, 103 + FIELD_PREP(TXGBE_RX_GEN_CTL3_LOS_TRSHLD0, 0x4)); 111 104 112 105 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20); 113 106 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46); ··· 161 172 162 173 int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 163 174 { 164 - int val, ret; 175 + int ret; 165 176 166 177 switch (interface) { 167 178 case PHY_INTERFACE_MODE_10GBASER: ··· 183 194 184 195 if (interface == PHY_INTERFACE_MODE_10GBASER) { 185 196 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR); 186 - val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1); 187 - val |= MDIO_CTRL1_SPEED10G; 188 - xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val); 197 + xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 198 + MDIO_CTRL1_SPEED10G, MDIO_CTRL1_SPEED10G); 189 199 txgbe_pma_config_10gbaser(xpcs); 190 200 } else { 191 201 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX);

+76 -95

drivers/net/pcs/pcs-xpcs.c

··· 175 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 176 } 177 177 178 + int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 + { 180 + return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 + } 182 + 178 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 179 184 u16 mask, u16 set) 180 185 { ··· 197 192 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 193 } 199 194 195 + static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 196 + u16 set) 197 + { 198 + return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 199 + } 200 + 200 201 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 201 202 { 202 203 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); ··· 211 200 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 201 { 213 202 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 203 + } 204 + 205 + static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 206 + { 207 + return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 214 208 } 215 209 216 210 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) ··· 342 326 return; 343 327 } 344 328 345 - ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 329 + ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 346 330 if (ret < 0) 347 331 goto out; 348 332 349 - ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); 333 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, DW_USXGMII_SS_MASK, 334 + speed_sel | DW_USXGMII_FULL); 350 335 if (ret < 0) 351 336 goto out; 352 337 353 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 354 - if (ret < 0) 355 - goto out; 356 - 357 - ret &= ~DW_USXGMII_SS_MASK; 358 - ret |= speed_sel | DW_USXGMII_FULL; 359 - 360 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 361 - if (ret < 0) 362 - goto out; 363 - 364 - ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 365 - if (ret < 0) 366 - goto out; 367 - 368 - ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); 338 + ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 339 + DW_USXGMII_RST); 369 340 if (ret < 0) 370 341 goto out; 371 342 ··· 416 413 if (ret < 0) 417 414 return ret; 418 415 419 - ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); 420 - if (ret < 0) 421 - return ret; 422 - 423 - ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; 424 - 425 - return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); 416 + return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 417 + MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 418 + MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 426 419 } 427 420 428 421 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, ··· 580 581 581 582 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) 582 583 { 584 + u16 mask, val; 583 585 int ret; 584 586 585 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); 586 - if (ret < 0) 587 - return ret; 587 + mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 588 + DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 589 + DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 590 + DW_VR_MII_EEE_MULT_FACT_100NS; 588 591 589 - if (enable) { 590 - /* Enable EEE */ 591 - ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 592 + if (enable) 593 + val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 592 594 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 593 595 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 594 596 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 595 597 mult_fact_100ns); 596 - } else { 597 - ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 598 - DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 599 - DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 600 - DW_VR_MII_EEE_MULT_FACT_100NS); 601 - } 602 - 603 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); 604 - if (ret < 0) 605 - return ret; 606 - 607 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); 608 - if (ret < 0) 609 - return ret; 610 - 611 - if (enable) 612 - ret |= DW_VR_MII_EEE_TRN_LPI; 613 598 else 614 - ret &= ~DW_VR_MII_EEE_TRN_LPI; 599 + val = 0; 615 600 616 - return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); 601 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 602 + val); 603 + if (ret < 0) 604 + return ret; 605 + 606 + return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 607 + DW_VR_MII_EEE_TRN_LPI, 608 + enable ? DW_VR_MII_EEE_TRN_LPI : 0); 617 609 } 618 610 EXPORT_SYMBOL_GPL(xpcs_config_eee); 619 611 ··· 636 646 unsigned int neg_mode) 637 647 { 638 648 int ret, mdio_ctrl, tx_conf; 649 + u16 mask, val; 639 650 640 651 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 641 652 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1); ··· 668 677 return ret; 669 678 } 670 679 671 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); 672 - if (ret < 0) 673 - return ret; 680 + mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 681 + val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 682 + DW_VR_MII_PCS_MODE_C37_SGMII); 674 683 675 - ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); 676 - ret |= FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 677 - DW_VR_MII_PCS_MODE_C37_SGMII); 678 684 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 679 - ret |= DW_VR_MII_AN_CTRL_8BIT; 685 + mask |= DW_VR_MII_AN_CTRL_8BIT; 686 + val |= DW_VR_MII_AN_CTRL_8BIT; 680 687 /* Hardware requires it to be PHY side SGMII */ 681 688 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 682 689 } else { 683 690 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 684 691 } 685 - ret |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 686 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 692 + 693 + val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 694 + 695 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 687 696 if (ret < 0) 688 697 return ret; 689 698 690 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); 691 - if (ret < 0) 692 - return ret; 693 - 699 + mask = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 694 700 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 695 - ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 696 - else 697 - ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 701 + val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 698 702 699 - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 700 - ret |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 703 + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 704 + mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 705 + val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 706 + } 701 707 702 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); 708 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 703 709 if (ret < 0) 704 710 return ret; 705 711 ··· 714 726 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 715 727 int ret, mdio_ctrl, adv; 716 728 bool changed = 0; 729 + u16 mask, val; 717 730 718 731 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 719 732 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1); ··· 735 746 return ret; 736 747 } 737 748 738 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); 739 - if (ret < 0) 740 - return ret; 749 + mask = DW_VR_MII_PCS_MODE_MASK; 750 + val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 751 + DW_VR_MII_PCS_MODE_C37_1000BASEX); 741 752 742 - ret &= ~DW_VR_MII_PCS_MODE_MASK; 743 - if (!xpcs->pcs.poll) 744 - ret |= DW_VR_MII_AN_INTR_EN; 745 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 753 + if (!xpcs->pcs.poll) { 754 + mask |= DW_VR_MII_AN_INTR_EN; 755 + val |= DW_VR_MII_AN_INTR_EN; 756 + } 757 + 758 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 746 759 if (ret < 0) 747 760 return ret; 748 761 ··· 781 790 { 782 791 int ret; 783 792 784 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); 785 - if (ret < 0) 786 - return ret; 787 - ret |= DW_VR_MII_DIG_CTRL1_2G5_EN; 788 - ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 789 - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); 793 + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 794 + DW_VR_MII_DIG_CTRL1_2G5_EN | 795 + DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 796 + DW_VR_MII_DIG_CTRL1_2G5_EN); 790 797 if (ret < 0) 791 798 return ret; 792 799 793 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 794 - if (ret < 0) 795 - return ret; 796 - ret &= ~AN_CL37_EN; 797 - ret |= SGMII_SPEED_SS6; 798 - ret &= ~SGMII_SPEED_SS13; 799 - return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret); 800 + return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 801 + AN_CL37_EN | SGMII_SPEED_SS6 | SGMII_SPEED_SS13, 802 + SGMII_SPEED_SS6); 800 803 } 801 804 802 805 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, ··· 1164 1179 static void xpcs_an_restart(struct phylink_pcs *pcs) 1165 1180 { 1166 1181 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1167 - int ret; 1168 1182 1169 - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 1170 - if (ret >= 0) { 1171 - ret |= BMCR_ANRESTART; 1172 - xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 1173 - } 1183 + xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, BMCR_ANRESTART, 1184 + BMCR_ANRESTART); 1174 1185 } 1175 1186 1176 1187 static int xpcs_read_ids(struct dw_xpcs *xpcs)

drivers/net/pcs/pcs-xpcs.h

··· 139 139 140 140 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); 141 141 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val); 142 + int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set); 142 143 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg); 143 144 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val); 144 145 int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);