tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

net: pcs: xpcs: use FIELD_PREP() and FIELD_GET()

Convert xpcs to use the bitfield macros rather than definining the
bitfield shifts and open-coding the insertion and extraction of these
bitfields.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Russell King (Oracle) and committed by
David S. Miller f6818918 7921d3e6

+6 -12
+6 -8
drivers/net/pcs/pcs-xpcs.c
··· 592 592 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 593 593 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 594 594 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 595 - mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT; 595 + FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 596 + mult_fact_100ns); 596 597 } else { 597 598 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 598 599 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | ··· 682 681 return ret; 683 682 684 683 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); 685 - ret |= (DW_VR_MII_PCS_MODE_C37_SGMII << 686 - DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT & 687 - DW_VR_MII_PCS_MODE_MASK); 684 + ret |= FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 685 + DW_VR_MII_PCS_MODE_C37_SGMII); 688 686 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 689 687 ret |= DW_VR_MII_AN_CTRL_8BIT; 690 688 /* Hardware requires it to be PHY side SGMII */ ··· 691 691 } else { 692 692 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 693 693 } 694 - ret |= tx_conf << DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT & 695 - DW_VR_MII_TX_CONFIG_MASK; 694 + ret |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 696 695 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 697 696 if (ret < 0) 698 697 return ret; ··· 970 971 971 972 state->link = true; 972 973 973 - speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >> 974 - DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT; 974 + speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 975 975 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 976 976 state->speed = SPEED_1000; 977 977 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
-4
drivers/net/pcs/pcs-xpcs.h
··· 77 77 78 78 /* VR_MII_AN_CTRL */ 79 79 #define DW_VR_MII_AN_CTRL_8BIT BIT(8) 80 - #define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3 81 80 #define DW_VR_MII_TX_CONFIG_MASK BIT(3) 82 81 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1 83 82 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0 84 - #define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1 85 83 #define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1) 86 84 #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 87 85 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 ··· 88 90 /* VR_MII_AN_INTR_STS */ 89 91 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0) 90 92 #define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1) 91 - #define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2 92 93 #define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2) 93 94 #define DW_VR_MII_C37_ANSGM_SP_10 0x0 94 95 #define DW_VR_MII_C37_ANSGM_SP_100 0x1 ··· 111 114 #define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */ 112 115 #define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */ 113 116 114 - #define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8 115 117 #define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8) 116 118 117 119 /* VR MII EEE Control 1 defines */