commit c919b371cb734f42b1130e706ecee262f8d9261d · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

drm/radeon/kms: avoid corner case issue with unmappable vram V2

We should not allocate any object into unmappable vram if we
have no means to access them which on all GPU means having the
CP running and on newer GPU having the blit utility working.

This patch limit the vram allocation to visible vram until
we have acceleration up and running.

Note that it's more than unlikely that we run into any issue
related to that as when acceleration is not woring userspace
should allocate any object in vram beside front buffer which
should fit in visible vram.

V2 use real_vram_size as mc_vram_size could be bigger than
the actual amount of vram

[airlied: fixup r700_cp_stop case]

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

authored by Jerome Glisse and committed by Dave Airlie 15 years ago c919b371 85a33188

+14 -1

9 changed files

expand all

unified split

drivers

gpu

drm

radeon

evergreen.c

r100.c

r600.c

r600_blit_kms.c

radeon.h

radeon_object.c

rs600.c

rs690.c

rv770.c

drivers/gpu/drm/radeon/evergreen.c

··· 1407 1407 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1408 1408 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1409 1409 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1410 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1410 1411 r600_vram_gtt_location(rdev, &rdev->mc); 1411 1412 radeon_update_bandwidth_info(rdev); 1412 1413

drivers/gpu/drm/radeon/r100.c

··· 1030 1030 return r; 1031 1031 } 1032 1032 rdev->cp.ready = true; 1033 + rdev->mc.active_vram_size = rdev->mc.real_vram_size; 1033 1034 return 0; 1034 1035 } 1035 1036 ··· 1048 1047 void r100_cp_disable(struct radeon_device *rdev) 1049 1048 { 1050 1049 /* Disable ring */ 1050 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1051 1051 rdev->cp.ready = false; 1052 1052 WREG32(RADEON_CP_CSQ_MODE, 0); 1053 1053 WREG32(RADEON_CP_CSQ_CNTL, 0); ··· 2297 2295 /* FIXME we don't use the second aperture yet when we could use it */ 2298 2296 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2299 2297 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2298 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2300 2299 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2301 2300 if (rdev->flags & RADEON_IS_IGP) { 2302 2301 uint32_t tom;

drivers/gpu/drm/radeon/r600.c

··· 1248 1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1249 1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1250 1250 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1251 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1251 1252 r600_vram_gtt_location(rdev, &rdev->mc); 1252 1253 1253 1254 if (rdev->flags & RADEON_IS_IGP) { ··· 1918 1917 */ 1919 1918 void r600_cp_stop(struct radeon_device *rdev) 1920 1919 { 1920 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1921 1921 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1922 1922 } 1923 1923

drivers/gpu/drm/radeon/r600_blit_kms.c

··· 532 532 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); 533 533 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 534 534 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 535 + rdev->mc.active_vram_size = rdev->mc.real_vram_size; 535 536 return 0; 536 537 } 537 538 ··· 540 539 { 541 540 int r; 542 541 542 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 543 543 if (rdev->r600_blit.shader_obj == NULL) 544 544 return; 545 545 /* If we can't reserve the bo, unref should be enough to destroy

drivers/gpu/drm/radeon/radeon.h

··· 344 344 * about vram size near mc fb location */ 345 345 u64 mc_vram_size; 346 346 u64 visible_vram_size; 347 + u64 active_vram_size; 347 348 u64 gtt_size; 348 349 u64 gtt_start; 349 350 u64 gtt_end;

+1 -1

drivers/gpu/drm/radeon/radeon_object.c

··· 69 69 u32 c = 0; 70 70 71 71 rbo->placement.fpfn = 0; 72 - rbo->placement.lpfn = 0; 72 + rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT; 73 73 rbo->placement.placement = rbo->placements; 74 74 rbo->placement.busy_placement = rbo->placements; 75 75 if (domain & RADEON_GEM_DOMAIN_VRAM)

drivers/gpu/drm/radeon/rs600.c

··· 693 693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 694 694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 695 695 rdev->mc.visible_vram_size = rdev->mc.aper_size; 696 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 696 697 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 697 698 base = RREG32_MC(R_000004_MC_FB_LOCATION); 698 699 base = G_000004_MC_FB_START(base) << 16;

drivers/gpu/drm/radeon/rs690.c

··· 157 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 158 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 159 159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 160 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 160 161 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 161 162 base = G_000100_MC_FB_START(base) << 16; 162 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);

drivers/gpu/drm/radeon/rv770.c

··· 267 267 */ 268 268 void r700_cp_stop(struct radeon_device *rdev) 269 269 { 270 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 270 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 271 272 } 272 273 ··· 993 992 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 994 993 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 995 994 rdev->mc.visible_vram_size = rdev->mc.aper_size; 995 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 996 996 r600_vram_gtt_location(rdev, &rdev->mc); 997 997 radeon_update_bandwidth_info(rdev); 998 998