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Merge tag 'zynqmp-dt-for-v5.11' of https://github.com/Xilinx/linux-xlnx into arm/dt
arm64: dts: ZynqMP DT changes for v5.11
- Wiring IPI communication channel with firmware driver
- Taking GIC to main bus to have only one
- Small fix in zynqmp.dtsi reported by dt_binding_check
* tag 'zynqmp-dt-for-v5.11' of https://github.com/Xilinx/linux-xlnx:
arm64: dts: zynqmp: Wire mailbox with zynqmp-power driver
arm64: dts: zynqmp: Fix pcie ranges description
arm64: zynqmp: Move gic node to axi bus
Link: https://lore.kernel.org/r/f460f6ac-d235-a33b-3d0f-ca904a43e687@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+39
-21
+39
-21
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+39
-21
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
···
99
99
};
100
100
};
101
101
102
+
zynqmp_ipi {
103
+
compatible = "xlnx,zynqmp-ipi-mailbox";
104
+
interrupt-parent = <&gic>;
105
+
interrupts = <0 35 4>;
106
+
xlnx,ipi-id = <0>;
107
+
#address-cells = <2>;
108
+
#size-cells = <2>;
109
+
ranges;
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+
111
+
ipi_mailbox_pmu1: mailbox@ff990400 {
112
+
reg = <0x0 0xff9905c0 0x0 0x20>,
113
+
<0x0 0xff9905e0 0x0 0x20>,
114
+
<0x0 0xff990e80 0x0 0x20>,
115
+
<0x0 0xff990ea0 0x0 0x20>;
116
+
reg-names = "local_request_region",
117
+
"local_response_region",
118
+
"remote_request_region",
119
+
"remote_response_region";
120
+
#mbox-cells = <1>;
121
+
xlnx,ipi-id = <4>;
122
+
};
123
+
};
124
+
102
125
dcc: dcc {
103
126
compatible = "arm,dcc";
104
127
status = "disabled";
···
151
128
compatible = "xlnx,zynqmp-power";
152
129
interrupt-parent = <&gic>;
153
130
interrupts = <0 35 4>;
131
+
mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
132
+
mbox-names = "tx", "rx";
154
133
};
155
134
156
135
zynqmp_clk: clock-controller {
···
205
180
#address-cells = <2>;
206
181
#size-cells = <2>;
207
182
ranges;
208
-
};
209
-
210
-
amba_apu: axi@0 {
211
-
compatible = "simple-bus";
212
-
#address-cells = <2>;
213
-
#size-cells = <1>;
214
-
ranges = <0 0 0 0 0xffffffff>;
215
-
216
-
gic: interrupt-controller@f9010000 {
217
-
compatible = "arm,gic-400";
218
-
#interrupt-cells = <3>;
219
-
reg = <0x0 0xf9010000 0x10000>,
220
-
<0x0 0xf9020000 0x20000>,
221
-
<0x0 0xf9040000 0x20000>,
222
-
<0x0 0xf9060000 0x20000>;
223
-
interrupt-controller;
224
-
interrupt-parent = <&gic>;
225
-
interrupts = <1 9 0xf04>;
226
-
};
227
183
};
228
184
229
185
amba: axi {
···
343
337
clock-names = "clk_main", "clk_apb";
344
338
xlnx,bus-width = <128>;
345
339
power-domains = <&zynqmp_firmware PD_GDMA>;
340
+
};
341
+
342
+
gic: interrupt-controller@f9010000 {
343
+
compatible = "arm,gic-400";
344
+
#interrupt-cells = <3>;
345
+
reg = <0x0 0xf9010000 0x0 0x10000>,
346
+
<0x0 0xf9020000 0x0 0x20000>,
347
+
<0x0 0xf9040000 0x0 0x20000>,
348
+
<0x0 0xf9060000 0x0 0x20000>;
349
+
interrupt-controller;
350
+
interrupt-parent = <&gic>;
351
+
interrupts = <1 9 0xf04>;
346
352
};
347
353
348
354
/* LPDDMA default allows only secured access. inorder to enable
···
560
542
<0x0 0xfd480000 0x0 0x1000>,
561
543
<0x80 0x00000000 0x0 0x1000000>;
562
544
reg-names = "breg", "pcireg", "cfg";
563
-
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
564
-
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
545
+
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
546
+
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
565
547
bus-range = <0x00 0xff>;
566
548
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
567
549
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,