drm/i915: Rename many remaining uses of "output" to encoder or connector.

Signed-off-by: Eric Anholt <eric@anholt.net>

+103 -98
+10 -10
drivers/gpu/drm/i915/intel_display.c
··· 754 return false; 755 } 756 757 - struct drm_connector * 758 - intel_pipe_get_output (struct drm_crtc *crtc) 759 { 760 struct drm_device *dev = crtc->dev; 761 struct drm_mode_config *mode_config = &dev->mode_config; ··· 2916 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; 2917 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; 2918 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 2919 - int refclk, num_outputs = 0; 2920 intel_clock_t clock, reduced_clock; 2921 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 2922 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; ··· 2974 break; 2975 } 2976 2977 - num_outputs++; 2978 } 2979 2980 - if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { 2981 refclk = dev_priv->lvds_ssc_freq * 1000; 2982 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 2983 refclk / 1000); ··· 3048 if (is_edp) { 3049 struct drm_connector *edp; 3050 target_clock = mode->clock; 3051 - edp = intel_pipe_get_output(crtc); 3052 intel_edp_link_config(to_intel_encoder(edp), 3053 &lane, &link_bw); 3054 } else { ··· 3230 /* XXX: just matching BIOS for now */ 3231 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3232 dpll |= 3; 3233 - else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) 3234 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3235 else 3236 dpll |= PLL_REF_INPUT_DREFCLK; ··· 3654 * detection. 3655 * 3656 * It will be up to the load-detect code to adjust the pipe as appropriate for 3657 - * its requirements. The pipe will be connected to no other outputs. 3658 * 3659 - * Currently this code will only succeed if there is a pipe with no outputs 3660 * configured for it. In the future, it could choose to temporarily disable 3661 * some outputs to free up a pipe for its use. 3662 * ··· 3770 drm_helper_disable_unused_functions(dev); 3771 } 3772 3773 - /* Switch crtc and output back off if necessary */ 3774 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { 3775 if (encoder->crtc == crtc) 3776 encoder_funcs->dpms(encoder, dpms_mode);
··· 754 return false; 755 } 756 757 + static struct drm_connector * 758 + intel_pipe_get_connector (struct drm_crtc *crtc) 759 { 760 struct drm_device *dev = crtc->dev; 761 struct drm_mode_config *mode_config = &dev->mode_config; ··· 2916 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; 2917 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; 2918 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 2919 + int refclk, num_connectors = 0; 2920 intel_clock_t clock, reduced_clock; 2921 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 2922 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; ··· 2974 break; 2975 } 2976 2977 + num_connectors++; 2978 } 2979 2980 + if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { 2981 refclk = dev_priv->lvds_ssc_freq * 1000; 2982 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 2983 refclk / 1000); ··· 3048 if (is_edp) { 3049 struct drm_connector *edp; 3050 target_clock = mode->clock; 3051 + edp = intel_pipe_get_connector(crtc); 3052 intel_edp_link_config(to_intel_encoder(edp), 3053 &lane, &link_bw); 3054 } else { ··· 3230 /* XXX: just matching BIOS for now */ 3231 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3232 dpll |= 3; 3233 + else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) 3234 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3235 else 3236 dpll |= PLL_REF_INPUT_DREFCLK; ··· 3654 * detection. 3655 * 3656 * It will be up to the load-detect code to adjust the pipe as appropriate for 3657 + * its requirements. The pipe will be connected to no other encoders. 3658 * 3659 + * Currently this code will only succeed if there is a pipe with no encoders 3660 * configured for it. In the future, it could choose to temporarily disable 3661 * some outputs to free up a pipe for its use. 3662 * ··· 3770 drm_helper_disable_unused_functions(dev); 3771 } 3772 3773 + /* Switch crtc and encoder back off if necessary */ 3774 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { 3775 if (encoder->crtc == crtc) 3776 encoder_funcs->dpms(encoder, dpms_mode);
+93 -88
drivers/gpu/drm/i915/intel_sdvo.c
··· 53 u8 slave_addr; 54 55 /* Register for the SDVO device: SDVOB or SDVOC */ 56 - int output_device; 57 58 /* Active outputs controlled by this SDVO output */ 59 uint16_t controlled_output; ··· 123 */ 124 struct intel_sdvo_encode encode; 125 126 - /* DDC bus used by this SDVO output */ 127 uint8_t ddc_bus; 128 129 /* Mac mini hack -- use the same DDC as the analog connector */ ··· 176 u32 bval = val, cval = val; 177 int i; 178 179 - if (sdvo_priv->output_device == SDVOB) { 180 cval = I915_READ(SDVOC); 181 } else { 182 bval = I915_READ(SDVOB); ··· 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 353 }; 354 355 - #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") 356 - #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) 357 358 static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd, 359 void *args, int args_len) ··· 712 } 713 714 static bool 715 - intel_sdvo_create_preferred_input_timing(struct intel_encoder *output, 716 uint16_t clock, 717 uint16_t width, 718 uint16_t height) 719 { 720 struct intel_sdvo_preferred_input_timing_args args; 721 - struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 722 uint8_t status; 723 724 memset(&args, 0, sizeof(args)); ··· 732 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) 733 args.scaled = 1; 734 735 - intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 736 &args, sizeof(args)); 737 - status = intel_sdvo_read_response(output, NULL, 0); 738 if (status != SDVO_CMD_STATUS_SUCCESS) 739 return false; 740 741 return true; 742 } 743 744 - static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *output, 745 struct intel_sdvo_dtd *dtd) 746 { 747 bool status; 748 749 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 750 NULL, 0); 751 752 - status = intel_sdvo_read_response(output, &dtd->part1, 753 sizeof(dtd->part1)); 754 if (status != SDVO_CMD_STATUS_SUCCESS) 755 return false; 756 757 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 758 NULL, 0); 759 760 - status = intel_sdvo_read_response(output, &dtd->part2, 761 sizeof(dtd->part2)); 762 if (status != SDVO_CMD_STATUS_SUCCESS) 763 return false; ··· 877 mode->flags |= DRM_MODE_FLAG_PVSYNC; 878 } 879 880 - static bool intel_sdvo_get_supp_encode(struct intel_encoder *output, 881 struct intel_sdvo_encode *encode) 882 { 883 uint8_t status; 884 885 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); 886 - status = intel_sdvo_read_response(output, encode, sizeof(*encode)); 887 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ 888 memset(encode, 0, sizeof(*encode)); 889 return false; ··· 892 return true; 893 } 894 895 - static bool intel_sdvo_set_encode(struct intel_encoder *output, uint8_t mode) 896 { 897 uint8_t status; 898 899 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1); 900 - status = intel_sdvo_read_response(output, NULL, 0); 901 902 return (status == SDVO_CMD_STATUS_SUCCESS); 903 } 904 905 - static bool intel_sdvo_set_colorimetry(struct intel_encoder *output, 906 uint8_t mode) 907 { 908 uint8_t status; 909 910 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 911 - status = intel_sdvo_read_response(output, NULL, 0); 912 913 return (status == SDVO_CMD_STATUS_SUCCESS); 914 } 915 916 #if 0 917 - static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *output) 918 { 919 int i, j; 920 uint8_t set_buf_index[2]; ··· 924 uint8_t buf[48]; 925 uint8_t *pos; 926 927 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); 928 - intel_sdvo_read_response(output, &av_split, 1); 929 930 for (i = 0; i <= av_split; i++) { 931 set_buf_index[0] = i; set_buf_index[1] = 0; 932 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, 933 set_buf_index, 2); 934 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 935 - intel_sdvo_read_response(output, &buf_size, 1); 936 937 pos = buf; 938 for (j = 0; j <= buf_size; j += 8) { 939 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA, 940 NULL, 0); 941 - intel_sdvo_read_response(output, pos, 8); 942 pos += 8; 943 } 944 } 945 } 946 #endif 947 948 - static void intel_sdvo_set_hdmi_buf(struct intel_encoder *output, int index, 949 - uint8_t *data, int8_t size, uint8_t tx_rate) 950 { 951 uint8_t set_buf_index[2]; 952 953 set_buf_index[0] = index; 954 set_buf_index[1] = 0; 955 956 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2); 957 958 for (; size > 0; size -= 8) { 959 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8); 960 data += 8; 961 } 962 963 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 964 } 965 966 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) ··· 1037 } __attribute__ ((packed)) u; 1038 } __attribute__((packed)); 1039 1040 - static void intel_sdvo_set_avi_infoframe(struct intel_encoder *output, 1041 struct drm_display_mode * mode) 1042 { 1043 struct dip_infoframe avi_if = { ··· 1048 1049 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 1050 4 + avi_if.len); 1051 - intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len, 1052 SDVO_HBUF_TX_VSYNC); 1053 } 1054 1055 - static void intel_sdvo_set_tv_format(struct intel_encoder *output) 1056 { 1057 1058 struct intel_sdvo_tv_format format; 1059 - struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1060 uint32_t format_map, i; 1061 uint8_t status; 1062 ··· 1070 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? 1071 sizeof(format) : sizeof(format_map)); 1072 1073 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, 1074 sizeof(format)); 1075 1076 - status = intel_sdvo_read_response(output, NULL, 0); 1077 if (status != SDVO_CMD_STATUS_SUCCESS) 1078 DRM_DEBUG_KMS("%s: Failed to set TV format\n", 1079 SDVO_NAME(sdvo_priv)); ··· 1083 struct drm_display_mode *mode, 1084 struct drm_display_mode *adjusted_mode) 1085 { 1086 - struct intel_encoder *output = enc_to_intel_encoder(encoder); 1087 - struct intel_sdvo_priv *dev_priv = output->dev_priv; 1088 1089 if (dev_priv->is_tv) { 1090 struct intel_sdvo_dtd output_dtd; ··· 1099 1100 /* Set output timings */ 1101 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1102 - intel_sdvo_set_target_output(output, 1103 dev_priv->controlled_output); 1104 - intel_sdvo_set_output_timing(output, &output_dtd); 1105 1106 /* Set the input timing to the screen. Assume always input 0. */ 1107 - intel_sdvo_set_target_input(output, true, false); 1108 1109 1110 - success = intel_sdvo_create_preferred_input_timing(output, 1111 mode->clock / 10, 1112 mode->hdisplay, 1113 mode->vdisplay); 1114 if (success) { 1115 struct intel_sdvo_dtd input_dtd; 1116 1117 - intel_sdvo_get_preferred_input_timing(output, 1118 &input_dtd); 1119 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1120 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; ··· 1137 intel_sdvo_get_dtd_from_mode(&output_dtd, 1138 dev_priv->sdvo_lvds_fixed_mode); 1139 1140 - intel_sdvo_set_target_output(output, 1141 dev_priv->controlled_output); 1142 - intel_sdvo_set_output_timing(output, &output_dtd); 1143 1144 /* Set the input timing to the screen. Assume always input 0. */ 1145 - intel_sdvo_set_target_input(output, true, false); 1146 1147 1148 success = intel_sdvo_create_preferred_input_timing( 1149 - output, 1150 mode->clock / 10, 1151 mode->hdisplay, 1152 mode->vdisplay); ··· 1154 if (success) { 1155 struct intel_sdvo_dtd input_dtd; 1156 1157 - intel_sdvo_get_preferred_input_timing(output, 1158 &input_dtd); 1159 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1160 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; ··· 1186 struct drm_i915_private *dev_priv = dev->dev_private; 1187 struct drm_crtc *crtc = encoder->crtc; 1188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1189 - struct intel_encoder *output = enc_to_intel_encoder(encoder); 1190 - struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1191 u32 sdvox = 0; 1192 int sdvo_pixel_multiply; 1193 struct intel_sdvo_in_out_map in_out; ··· 1206 in_out.in0 = sdvo_priv->controlled_output; 1207 in_out.in1 = 0; 1208 1209 - intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP, 1210 &in_out, sizeof(in_out)); 1211 - status = intel_sdvo_read_response(output, NULL, 0); 1212 1213 if (sdvo_priv->is_hdmi) { 1214 - intel_sdvo_set_avi_infoframe(output, mode); 1215 sdvox |= SDVO_AUDIO_ENABLE; 1216 } 1217 ··· 1228 */ 1229 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { 1230 /* Set the output timing to the screen */ 1231 - intel_sdvo_set_target_output(output, 1232 sdvo_priv->controlled_output); 1233 - intel_sdvo_set_output_timing(output, &input_dtd); 1234 } 1235 1236 /* Set the input timing to the screen. Assume always input 0. */ 1237 - intel_sdvo_set_target_input(output, true, false); 1238 1239 if (sdvo_priv->is_tv) 1240 - intel_sdvo_set_tv_format(output); 1241 1242 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1243 * provide the device with a timing it can support, if it supports that ··· 1245 * output the preferred timing, and we don't support that currently. 1246 */ 1247 #if 0 1248 - success = intel_sdvo_create_preferred_input_timing(output, clock, 1249 width, height); 1250 if (success) { 1251 struct intel_sdvo_dtd *input_dtd; 1252 1253 - intel_sdvo_get_preferred_input_timing(output, &input_dtd); 1254 - intel_sdvo_set_input_timing(output, &input_dtd); 1255 } 1256 #else 1257 - intel_sdvo_set_input_timing(output, &input_dtd); 1258 #endif 1259 1260 switch (intel_sdvo_get_pixel_multiplier(mode)) { 1261 case 1: 1262 - intel_sdvo_set_clock_rate_mult(output, 1263 SDVO_CLOCK_RATE_MULT_1X); 1264 break; 1265 case 2: 1266 - intel_sdvo_set_clock_rate_mult(output, 1267 SDVO_CLOCK_RATE_MULT_2X); 1268 break; 1269 case 4: 1270 - intel_sdvo_set_clock_rate_mult(output, 1271 SDVO_CLOCK_RATE_MULT_4X); 1272 break; 1273 } ··· 1278 SDVO_VSYNC_ACTIVE_HIGH | 1279 SDVO_HSYNC_ACTIVE_HIGH; 1280 } else { 1281 - sdvox |= I915_READ(sdvo_priv->output_device); 1282 - switch (sdvo_priv->output_device) { 1283 case SDVOB: 1284 sdvox &= SDVOB_PRESERVE_MASK; 1285 break; ··· 1303 1304 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) 1305 sdvox |= SDVO_STALL_SELECT; 1306 - intel_sdvo_write_sdvox(output, sdvox); 1307 } 1308 1309 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) ··· 1320 intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1321 1322 if (mode == DRM_MODE_DPMS_OFF) { 1323 - temp = I915_READ(sdvo_priv->output_device); 1324 if ((temp & SDVO_ENABLE) != 0) { 1325 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE); 1326 } ··· 1330 int i; 1331 u8 status; 1332 1333 - temp = I915_READ(sdvo_priv->output_device); 1334 if ((temp & SDVO_ENABLE) == 0) 1335 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE); 1336 for (i = 0; i < 2; i++) ··· 1393 /* XXX: Save TV format/enhancements. */ 1394 } 1395 1396 - sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device); 1397 } 1398 1399 static void intel_sdvo_restore(struct drm_connector *connector) ··· 1504 1505 sdvo = iout->dev_priv; 1506 1507 - if (sdvo->output_device == SDVOB && sdvoB) 1508 return connector; 1509 1510 - if (sdvo->output_device == SDVOC && !sdvoB) 1511 return connector; 1512 1513 } ··· 2253 }; 2254 2255 static u8 2256 - intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device) 2257 { 2258 struct drm_i915_private *dev_priv = dev->dev_private; 2259 struct sdvo_device_mapping *my_mapping, *other_mapping; 2260 2261 - if (output_device == SDVOB) { 2262 my_mapping = &dev_priv->sdvo_mappings[0]; 2263 other_mapping = &dev_priv->sdvo_mappings[1]; 2264 } else { ··· 2283 /* No SDVO device info is found for another DVO port, 2284 * so use mapping assumption we had before BIOS parsing. 2285 */ 2286 - if (output_device == SDVOB) 2287 return 0x70; 2288 else 2289 return 0x72; ··· 2769 return; 2770 } 2771 2772 - bool intel_sdvo_init(struct drm_device *dev, int output_device) 2773 { 2774 struct drm_i915_private *dev_priv = dev->dev_private; 2775 struct drm_connector *connector; ··· 2785 } 2786 2787 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1); 2788 - sdvo_priv->output_device = output_device; 2789 2790 intel_encoder->dev_priv = sdvo_priv; 2791 intel_encoder->type = INTEL_OUTPUT_SDVO; 2792 2793 /* setup the DDC bus. */ 2794 - if (output_device == SDVOB) 2795 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); 2796 else 2797 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); ··· 2799 if (!intel_encoder->i2c_bus) 2800 goto err_inteloutput; 2801 2802 - sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device); 2803 2804 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2805 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; ··· 2808 for (i = 0; i < 0x40; i++) { 2809 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) { 2810 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2811 - output_device == SDVOB ? 'B' : 'C'); 2812 goto err_i2c; 2813 } 2814 } 2815 2816 /* setup the DDC bus. */ 2817 - if (output_device == SDVOB) { 2818 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); 2819 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2820 "SDVOB/VGA DDC BUS"); ··· 2838 if (intel_sdvo_output_setup(intel_encoder, 2839 sdvo_priv->caps.output_flags) != true) { 2840 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2841 - output_device == SDVOB ? 'B' : 'C'); 2842 goto err_i2c; 2843 } 2844
··· 53 u8 slave_addr; 54 55 /* Register for the SDVO device: SDVOB or SDVOC */ 56 + int sdvo_reg; 57 58 /* Active outputs controlled by this SDVO output */ 59 uint16_t controlled_output; ··· 123 */ 124 struct intel_sdvo_encode encode; 125 126 + /* DDC bus used by this SDVO encoder */ 127 uint8_t ddc_bus; 128 129 /* Mac mini hack -- use the same DDC as the analog connector */ ··· 176 u32 bval = val, cval = val; 177 int i; 178 179 + if (sdvo_priv->sdvo_reg == SDVOB) { 180 cval = I915_READ(SDVOC); 181 } else { 182 bval = I915_READ(SDVOB); ··· 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 353 }; 354 355 + #define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC") 356 + #define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv) 357 358 static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd, 359 void *args, int args_len) ··· 712 } 713 714 static bool 715 + intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder, 716 uint16_t clock, 717 uint16_t width, 718 uint16_t height) 719 { 720 struct intel_sdvo_preferred_input_timing_args args; 721 + struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 722 uint8_t status; 723 724 memset(&args, 0, sizeof(args)); ··· 732 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) 733 args.scaled = 1; 734 735 + intel_sdvo_write_cmd(intel_encoder, 736 + SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 737 &args, sizeof(args)); 738 + status = intel_sdvo_read_response(intel_encoder, NULL, 0); 739 if (status != SDVO_CMD_STATUS_SUCCESS) 740 return false; 741 742 return true; 743 } 744 745 + static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder, 746 struct intel_sdvo_dtd *dtd) 747 { 748 bool status; 749 750 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 751 NULL, 0); 752 753 + status = intel_sdvo_read_response(intel_encoder, &dtd->part1, 754 sizeof(dtd->part1)); 755 if (status != SDVO_CMD_STATUS_SUCCESS) 756 return false; 757 758 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 759 NULL, 0); 760 761 + status = intel_sdvo_read_response(intel_encoder, &dtd->part2, 762 sizeof(dtd->part2)); 763 if (status != SDVO_CMD_STATUS_SUCCESS) 764 return false; ··· 876 mode->flags |= DRM_MODE_FLAG_PVSYNC; 877 } 878 879 + static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder, 880 struct intel_sdvo_encode *encode) 881 { 882 uint8_t status; 883 884 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); 885 + status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode)); 886 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ 887 memset(encode, 0, sizeof(*encode)); 888 return false; ··· 891 return true; 892 } 893 894 + static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder, 895 + uint8_t mode) 896 { 897 uint8_t status; 898 899 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1); 900 + status = intel_sdvo_read_response(intel_encoder, NULL, 0); 901 902 return (status == SDVO_CMD_STATUS_SUCCESS); 903 } 904 905 + static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder, 906 uint8_t mode) 907 { 908 uint8_t status; 909 910 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 911 + status = intel_sdvo_read_response(intel_encoder, NULL, 0); 912 913 return (status == SDVO_CMD_STATUS_SUCCESS); 914 } 915 916 #if 0 917 + static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder) 918 { 919 int i, j; 920 uint8_t set_buf_index[2]; ··· 922 uint8_t buf[48]; 923 uint8_t *pos; 924 925 + intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); 926 + intel_sdvo_read_response(encoder, &av_split, 1); 927 928 for (i = 0; i <= av_split; i++) { 929 set_buf_index[0] = i; set_buf_index[1] = 0; 930 + intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 931 set_buf_index, 2); 932 + intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 933 + intel_sdvo_read_response(encoder, &buf_size, 1); 934 935 pos = buf; 936 for (j = 0; j <= buf_size; j += 8) { 937 + intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 938 NULL, 0); 939 + intel_sdvo_read_response(encoder, pos, 8); 940 pos += 8; 941 } 942 } 943 } 944 #endif 945 946 + static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder, 947 + int index, 948 + uint8_t *data, int8_t size, uint8_t tx_rate) 949 { 950 uint8_t set_buf_index[2]; 951 952 set_buf_index[0] = index; 953 set_buf_index[1] = 0; 954 955 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX, 956 + set_buf_index, 2); 957 958 for (; size > 0; size -= 8) { 959 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8); 960 data += 8; 961 } 962 963 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 964 } 965 966 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) ··· 1033 } __attribute__ ((packed)) u; 1034 } __attribute__((packed)); 1035 1036 + static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder, 1037 struct drm_display_mode * mode) 1038 { 1039 struct dip_infoframe avi_if = { ··· 1044 1045 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 1046 4 + avi_if.len); 1047 + intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if, 1048 + 4 + avi_if.len, 1049 SDVO_HBUF_TX_VSYNC); 1050 } 1051 1052 + static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder) 1053 { 1054 1055 struct intel_sdvo_tv_format format; 1056 + struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1057 uint32_t format_map, i; 1058 uint8_t status; 1059 ··· 1065 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? 1066 sizeof(format) : sizeof(format_map)); 1067 1068 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map, 1069 sizeof(format)); 1070 1071 + status = intel_sdvo_read_response(intel_encoder, NULL, 0); 1072 if (status != SDVO_CMD_STATUS_SUCCESS) 1073 DRM_DEBUG_KMS("%s: Failed to set TV format\n", 1074 SDVO_NAME(sdvo_priv)); ··· 1078 struct drm_display_mode *mode, 1079 struct drm_display_mode *adjusted_mode) 1080 { 1081 + struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1082 + struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv; 1083 1084 if (dev_priv->is_tv) { 1085 struct intel_sdvo_dtd output_dtd; ··· 1094 1095 /* Set output timings */ 1096 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1097 + intel_sdvo_set_target_output(intel_encoder, 1098 dev_priv->controlled_output); 1099 + intel_sdvo_set_output_timing(intel_encoder, &output_dtd); 1100 1101 /* Set the input timing to the screen. Assume always input 0. */ 1102 + intel_sdvo_set_target_input(intel_encoder, true, false); 1103 1104 1105 + success = intel_sdvo_create_preferred_input_timing(intel_encoder, 1106 mode->clock / 10, 1107 mode->hdisplay, 1108 mode->vdisplay); 1109 if (success) { 1110 struct intel_sdvo_dtd input_dtd; 1111 1112 + intel_sdvo_get_preferred_input_timing(intel_encoder, 1113 &input_dtd); 1114 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1115 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; ··· 1132 intel_sdvo_get_dtd_from_mode(&output_dtd, 1133 dev_priv->sdvo_lvds_fixed_mode); 1134 1135 + intel_sdvo_set_target_output(intel_encoder, 1136 dev_priv->controlled_output); 1137 + intel_sdvo_set_output_timing(intel_encoder, &output_dtd); 1138 1139 /* Set the input timing to the screen. Assume always input 0. */ 1140 + intel_sdvo_set_target_input(intel_encoder, true, false); 1141 1142 1143 success = intel_sdvo_create_preferred_input_timing( 1144 + intel_encoder, 1145 mode->clock / 10, 1146 mode->hdisplay, 1147 mode->vdisplay); ··· 1149 if (success) { 1150 struct intel_sdvo_dtd input_dtd; 1151 1152 + intel_sdvo_get_preferred_input_timing(intel_encoder, 1153 &input_dtd); 1154 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1155 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; ··· 1181 struct drm_i915_private *dev_priv = dev->dev_private; 1182 struct drm_crtc *crtc = encoder->crtc; 1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1184 + struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1185 + struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1186 u32 sdvox = 0; 1187 int sdvo_pixel_multiply; 1188 struct intel_sdvo_in_out_map in_out; ··· 1201 in_out.in0 = sdvo_priv->controlled_output; 1202 in_out.in1 = 0; 1203 1204 + intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP, 1205 &in_out, sizeof(in_out)); 1206 + status = intel_sdvo_read_response(intel_encoder, NULL, 0); 1207 1208 if (sdvo_priv->is_hdmi) { 1209 + intel_sdvo_set_avi_infoframe(intel_encoder, mode); 1210 sdvox |= SDVO_AUDIO_ENABLE; 1211 } 1212 ··· 1223 */ 1224 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { 1225 /* Set the output timing to the screen */ 1226 + intel_sdvo_set_target_output(intel_encoder, 1227 sdvo_priv->controlled_output); 1228 + intel_sdvo_set_output_timing(intel_encoder, &input_dtd); 1229 } 1230 1231 /* Set the input timing to the screen. Assume always input 0. */ 1232 + intel_sdvo_set_target_input(intel_encoder, true, false); 1233 1234 if (sdvo_priv->is_tv) 1235 + intel_sdvo_set_tv_format(intel_encoder); 1236 1237 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1238 * provide the device with a timing it can support, if it supports that ··· 1240 * output the preferred timing, and we don't support that currently. 1241 */ 1242 #if 0 1243 + success = intel_sdvo_create_preferred_input_timing(encoder, clock, 1244 width, height); 1245 if (success) { 1246 struct intel_sdvo_dtd *input_dtd; 1247 1248 + intel_sdvo_get_preferred_input_timing(encoder, &input_dtd); 1249 + intel_sdvo_set_input_timing(encoder, &input_dtd); 1250 } 1251 #else 1252 + intel_sdvo_set_input_timing(intel_encoder, &input_dtd); 1253 #endif 1254 1255 switch (intel_sdvo_get_pixel_multiplier(mode)) { 1256 case 1: 1257 + intel_sdvo_set_clock_rate_mult(intel_encoder, 1258 SDVO_CLOCK_RATE_MULT_1X); 1259 break; 1260 case 2: 1261 + intel_sdvo_set_clock_rate_mult(intel_encoder, 1262 SDVO_CLOCK_RATE_MULT_2X); 1263 break; 1264 case 4: 1265 + intel_sdvo_set_clock_rate_mult(intel_encoder, 1266 SDVO_CLOCK_RATE_MULT_4X); 1267 break; 1268 } ··· 1273 SDVO_VSYNC_ACTIVE_HIGH | 1274 SDVO_HSYNC_ACTIVE_HIGH; 1275 } else { 1276 + sdvox |= I915_READ(sdvo_priv->sdvo_reg); 1277 + switch (sdvo_priv->sdvo_reg) { 1278 case SDVOB: 1279 sdvox &= SDVOB_PRESERVE_MASK; 1280 break; ··· 1298 1299 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) 1300 sdvox |= SDVO_STALL_SELECT; 1301 + intel_sdvo_write_sdvox(intel_encoder, sdvox); 1302 } 1303 1304 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) ··· 1315 intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1316 1317 if (mode == DRM_MODE_DPMS_OFF) { 1318 + temp = I915_READ(sdvo_priv->sdvo_reg); 1319 if ((temp & SDVO_ENABLE) != 0) { 1320 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE); 1321 } ··· 1325 int i; 1326 u8 status; 1327 1328 + temp = I915_READ(sdvo_priv->sdvo_reg); 1329 if ((temp & SDVO_ENABLE) == 0) 1330 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE); 1331 for (i = 0; i < 2; i++) ··· 1388 /* XXX: Save TV format/enhancements. */ 1389 } 1390 1391 + sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg); 1392 } 1393 1394 static void intel_sdvo_restore(struct drm_connector *connector) ··· 1499 1500 sdvo = iout->dev_priv; 1501 1502 + if (sdvo->sdvo_reg == SDVOB && sdvoB) 1503 return connector; 1504 1505 + if (sdvo->sdvo_reg == SDVOC && !sdvoB) 1506 return connector; 1507 1508 } ··· 2248 }; 2249 2250 static u8 2251 + intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) 2252 { 2253 struct drm_i915_private *dev_priv = dev->dev_private; 2254 struct sdvo_device_mapping *my_mapping, *other_mapping; 2255 2256 + if (sdvo_reg == SDVOB) { 2257 my_mapping = &dev_priv->sdvo_mappings[0]; 2258 other_mapping = &dev_priv->sdvo_mappings[1]; 2259 } else { ··· 2278 /* No SDVO device info is found for another DVO port, 2279 * so use mapping assumption we had before BIOS parsing. 2280 */ 2281 + if (sdvo_reg == SDVOB) 2282 return 0x70; 2283 else 2284 return 0x72; ··· 2764 return; 2765 } 2766 2767 + bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2768 { 2769 struct drm_i915_private *dev_priv = dev->dev_private; 2770 struct drm_connector *connector; ··· 2780 } 2781 2782 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1); 2783 + sdvo_priv->sdvo_reg = sdvo_reg; 2784 2785 intel_encoder->dev_priv = sdvo_priv; 2786 intel_encoder->type = INTEL_OUTPUT_SDVO; 2787 2788 /* setup the DDC bus. */ 2789 + if (sdvo_reg == SDVOB) 2790 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); 2791 else 2792 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); ··· 2794 if (!intel_encoder->i2c_bus) 2795 goto err_inteloutput; 2796 2797 + sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); 2798 2799 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2800 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; ··· 2803 for (i = 0; i < 0x40; i++) { 2804 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) { 2805 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2806 + sdvo_reg == SDVOB ? 'B' : 'C'); 2807 goto err_i2c; 2808 } 2809 } 2810 2811 /* setup the DDC bus. */ 2812 + if (sdvo_reg == SDVOB) { 2813 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); 2814 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2815 "SDVOB/VGA DDC BUS"); ··· 2833 if (intel_sdvo_output_setup(intel_encoder, 2834 sdvo_priv->caps.output_flags) != true) { 2835 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2836 + sdvo_reg == SDVOB ? 'B' : 'C'); 2837 goto err_i2c; 2838 } 2839