···754754 return false;755755}756756757757-struct drm_connector *758758-intel_pipe_get_output (struct drm_crtc *crtc)757757+static struct drm_connector *758758+intel_pipe_get_connector (struct drm_crtc *crtc)759759{760760 struct drm_device *dev = crtc->dev;761761 struct drm_mode_config *mode_config = &dev->mode_config;···29162916 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;29172917 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;29182918 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;29192919- int refclk, num_outputs = 0;29192919+ int refclk, num_connectors = 0;29202920 intel_clock_t clock, reduced_clock;29212921 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;29222922 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;···29742974 break;29752975 }2976297629772977- num_outputs++;29772977+ num_connectors++;29782978 }2979297929802980- if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {29802980+ if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {29812981 refclk = dev_priv->lvds_ssc_freq * 1000;29822982 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",29832983 refclk / 1000);···30483048 if (is_edp) {30493049 struct drm_connector *edp;30503050 target_clock = mode->clock;30513051- edp = intel_pipe_get_output(crtc);30513051+ edp = intel_pipe_get_connector(crtc);30523052 intel_edp_link_config(to_intel_encoder(edp),30533053 &lane, &link_bw);30543054 } else {···32303230 /* XXX: just matching BIOS for now */32313231 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */32323232 dpll |= 3;32333233- else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)32333233+ else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)32343234 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;32353235 else32363236 dpll |= PLL_REF_INPUT_DREFCLK;···36543654 * detection.36553655 *36563656 * It will be up to the load-detect code to adjust the pipe as appropriate for36573657- * its requirements. The pipe will be connected to no other outputs.36573657+ * its requirements. The pipe will be connected to no other encoders.36583658 *36593659- * Currently this code will only succeed if there is a pipe with no outputs36593659+ * Currently this code will only succeed if there is a pipe with no encoders36603660 * configured for it. In the future, it could choose to temporarily disable36613661 * some outputs to free up a pipe for its use.36623662 *···37703770 drm_helper_disable_unused_functions(dev);37713771 }3772377237733773- /* Switch crtc and output back off if necessary */37733773+ /* Switch crtc and encoder back off if necessary */37743774 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {37753775 if (encoder->crtc == crtc)37763776 encoder_funcs->dpms(encoder, dpms_mode);
+93-88
drivers/gpu/drm/i915/intel_sdvo.c
···5353 u8 slave_addr;54545555 /* Register for the SDVO device: SDVOB or SDVOC */5656- int output_device;5656+ int sdvo_reg;57575858 /* Active outputs controlled by this SDVO output */5959 uint16_t controlled_output;···123123 */124124 struct intel_sdvo_encode encode;125125126126- /* DDC bus used by this SDVO output */126126+ /* DDC bus used by this SDVO encoder */127127 uint8_t ddc_bus;128128129129 /* Mac mini hack -- use the same DDC as the analog connector */···176176 u32 bval = val, cval = val;177177 int i;178178179179- if (sdvo_priv->output_device == SDVOB) {179179+ if (sdvo_priv->sdvo_reg == SDVOB) {180180 cval = I915_READ(SDVOC);181181 } else {182182 bval = I915_READ(SDVOB);···352352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),353353};354354355355-#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")356356-#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)355355+#define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")356356+#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)357357358358static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,359359 void *args, int args_len)···712712}713713714714static bool715715-intel_sdvo_create_preferred_input_timing(struct intel_encoder *output,715715+intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,716716 uint16_t clock,717717 uint16_t width,718718 uint16_t height)719719{720720 struct intel_sdvo_preferred_input_timing_args args;721721- struct intel_sdvo_priv *sdvo_priv = output->dev_priv;721721+ struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;722722 uint8_t status;723723724724 memset(&args, 0, sizeof(args));···732732 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))733733 args.scaled = 1;734734735735- intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,735735+ intel_sdvo_write_cmd(intel_encoder,736736+ SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,736737 &args, sizeof(args));737737- status = intel_sdvo_read_response(output, NULL, 0);738738+ status = intel_sdvo_read_response(intel_encoder, NULL, 0);738739 if (status != SDVO_CMD_STATUS_SUCCESS)739740 return false;740741741742 return true;742743}743744744744-static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *output,745745+static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,745746 struct intel_sdvo_dtd *dtd)746747{747748 bool status;748749749749- intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,750750+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,750751 NULL, 0);751752752752- status = intel_sdvo_read_response(output, &dtd->part1,753753+ status = intel_sdvo_read_response(intel_encoder, &dtd->part1,753754 sizeof(dtd->part1));754755 if (status != SDVO_CMD_STATUS_SUCCESS)755756 return false;756757757757- intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,758758+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,758759 NULL, 0);759760760760- status = intel_sdvo_read_response(output, &dtd->part2,761761+ status = intel_sdvo_read_response(intel_encoder, &dtd->part2,761762 sizeof(dtd->part2));762763 if (status != SDVO_CMD_STATUS_SUCCESS)763764 return false;···877876 mode->flags |= DRM_MODE_FLAG_PVSYNC;878877}879878880880-static bool intel_sdvo_get_supp_encode(struct intel_encoder *output,879879+static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,881880 struct intel_sdvo_encode *encode)882881{883882 uint8_t status;884883885885- intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);886886- status = intel_sdvo_read_response(output, encode, sizeof(*encode));884884+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);885885+ status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));887886 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */888887 memset(encode, 0, sizeof(*encode));889888 return false;···892891 return true;893892}894893895895-static bool intel_sdvo_set_encode(struct intel_encoder *output, uint8_t mode)894894+static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,895895+ uint8_t mode)896896{897897 uint8_t status;898898899899- intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);900900- status = intel_sdvo_read_response(output, NULL, 0);899899+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);900900+ status = intel_sdvo_read_response(intel_encoder, NULL, 0);901901902902 return (status == SDVO_CMD_STATUS_SUCCESS);903903}904904905905-static bool intel_sdvo_set_colorimetry(struct intel_encoder *output,905905+static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,906906 uint8_t mode)907907{908908 uint8_t status;909909910910- intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);911911- status = intel_sdvo_read_response(output, NULL, 0);910910+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);911911+ status = intel_sdvo_read_response(intel_encoder, NULL, 0);912912913913 return (status == SDVO_CMD_STATUS_SUCCESS);914914}915915916916#if 0917917-static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *output)917917+static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)918918{919919 int i, j;920920 uint8_t set_buf_index[2];···924922 uint8_t buf[48];925923 uint8_t *pos;926924927927- intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);928928- intel_sdvo_read_response(output, &av_split, 1);925925+ intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);926926+ intel_sdvo_read_response(encoder, &av_split, 1);929927930928 for (i = 0; i <= av_split; i++) {931929 set_buf_index[0] = i; set_buf_index[1] = 0;932932- intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,930930+ intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,933931 set_buf_index, 2);934934- intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);935935- intel_sdvo_read_response(output, &buf_size, 1);932932+ intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);933933+ intel_sdvo_read_response(encoder, &buf_size, 1);936934937935 pos = buf;938936 for (j = 0; j <= buf_size; j += 8) {939939- intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,937937+ intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,940938 NULL, 0);941941- intel_sdvo_read_response(output, pos, 8);939939+ intel_sdvo_read_response(encoder, pos, 8);942940 pos += 8;943941 }944942 }945943}946944#endif947945948948-static void intel_sdvo_set_hdmi_buf(struct intel_encoder *output, int index,949949- uint8_t *data, int8_t size, uint8_t tx_rate)946946+static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,947947+ int index,948948+ uint8_t *data, int8_t size, uint8_t tx_rate)950949{951950 uint8_t set_buf_index[2];952951953952 set_buf_index[0] = index;954953 set_buf_index[1] = 0;955954956956- intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);955955+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,956956+ set_buf_index, 2);957957958958 for (; size > 0; size -= 8) {959959- intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);959959+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);960960 data += 8;961961 }962962963963- intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);963963+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);964964}965965966966static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)···10371033 } __attribute__ ((packed)) u;10381034} __attribute__((packed));1039103510401040-static void intel_sdvo_set_avi_infoframe(struct intel_encoder *output,10361036+static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,10411037 struct drm_display_mode * mode)10421038{10431039 struct dip_infoframe avi_if = {···1048104410491045 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,10501046 4 + avi_if.len);10511051- intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,10471047+ intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,10481048+ 4 + avi_if.len,10521049 SDVO_HBUF_TX_VSYNC);10531050}1054105110551055-static void intel_sdvo_set_tv_format(struct intel_encoder *output)10521052+static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)10561053{1057105410581055 struct intel_sdvo_tv_format format;10591059- struct intel_sdvo_priv *sdvo_priv = output->dev_priv;10561056+ struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;10601057 uint32_t format_map, i;10611058 uint8_t status;10621059···10701065 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?10711066 sizeof(format) : sizeof(format_map));1072106710731073- intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,10681068+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,10741069 sizeof(format));1075107010761076- status = intel_sdvo_read_response(output, NULL, 0);10711071+ status = intel_sdvo_read_response(intel_encoder, NULL, 0);10771072 if (status != SDVO_CMD_STATUS_SUCCESS)10781073 DRM_DEBUG_KMS("%s: Failed to set TV format\n",10791074 SDVO_NAME(sdvo_priv));···10831078 struct drm_display_mode *mode,10841079 struct drm_display_mode *adjusted_mode)10851080{10861086- struct intel_encoder *output = enc_to_intel_encoder(encoder);10871087- struct intel_sdvo_priv *dev_priv = output->dev_priv;10811081+ struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);10821082+ struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;1088108310891084 if (dev_priv->is_tv) {10901085 struct intel_sdvo_dtd output_dtd;···1099109411001095 /* Set output timings */11011096 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);11021102- intel_sdvo_set_target_output(output,10971097+ intel_sdvo_set_target_output(intel_encoder,11031098 dev_priv->controlled_output);11041104- intel_sdvo_set_output_timing(output, &output_dtd);10991099+ intel_sdvo_set_output_timing(intel_encoder, &output_dtd);1105110011061101 /* Set the input timing to the screen. Assume always input 0. */11071107- intel_sdvo_set_target_input(output, true, false);11021102+ intel_sdvo_set_target_input(intel_encoder, true, false);110811031109110411101110- success = intel_sdvo_create_preferred_input_timing(output,11051105+ success = intel_sdvo_create_preferred_input_timing(intel_encoder,11111106 mode->clock / 10,11121107 mode->hdisplay,11131108 mode->vdisplay);11141109 if (success) {11151110 struct intel_sdvo_dtd input_dtd;1116111111171117- intel_sdvo_get_preferred_input_timing(output,11121112+ intel_sdvo_get_preferred_input_timing(intel_encoder,11181113 &input_dtd);11191114 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);11201115 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;···11371132 intel_sdvo_get_dtd_from_mode(&output_dtd,11381133 dev_priv->sdvo_lvds_fixed_mode);1139113411401140- intel_sdvo_set_target_output(output,11351135+ intel_sdvo_set_target_output(intel_encoder,11411136 dev_priv->controlled_output);11421142- intel_sdvo_set_output_timing(output, &output_dtd);11371137+ intel_sdvo_set_output_timing(intel_encoder, &output_dtd);1143113811441139 /* Set the input timing to the screen. Assume always input 0. */11451145- intel_sdvo_set_target_input(output, true, false);11401140+ intel_sdvo_set_target_input(intel_encoder, true, false);114611411147114211481143 success = intel_sdvo_create_preferred_input_timing(11491149- output,11441144+ intel_encoder,11501145 mode->clock / 10,11511146 mode->hdisplay,11521147 mode->vdisplay);···11541149 if (success) {11551150 struct intel_sdvo_dtd input_dtd;1156115111571157- intel_sdvo_get_preferred_input_timing(output,11521152+ intel_sdvo_get_preferred_input_timing(intel_encoder,11581153 &input_dtd);11591154 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);11601155 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;···11861181 struct drm_i915_private *dev_priv = dev->dev_private;11871182 struct drm_crtc *crtc = encoder->crtc;11881183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);11891189- struct intel_encoder *output = enc_to_intel_encoder(encoder);11901190- struct intel_sdvo_priv *sdvo_priv = output->dev_priv;11841184+ struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);11851185+ struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;11911186 u32 sdvox = 0;11921187 int sdvo_pixel_multiply;11931188 struct intel_sdvo_in_out_map in_out;···12061201 in_out.in0 = sdvo_priv->controlled_output;12071202 in_out.in1 = 0;1208120312091209- intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,12041204+ intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,12101205 &in_out, sizeof(in_out));12111211- status = intel_sdvo_read_response(output, NULL, 0);12061206+ status = intel_sdvo_read_response(intel_encoder, NULL, 0);1212120712131208 if (sdvo_priv->is_hdmi) {12141214- intel_sdvo_set_avi_infoframe(output, mode);12091209+ intel_sdvo_set_avi_infoframe(intel_encoder, mode);12151210 sdvox |= SDVO_AUDIO_ENABLE;12161211 }12171212···12281223 */12291224 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {12301225 /* Set the output timing to the screen */12311231- intel_sdvo_set_target_output(output,12261226+ intel_sdvo_set_target_output(intel_encoder,12321227 sdvo_priv->controlled_output);12331233- intel_sdvo_set_output_timing(output, &input_dtd);12281228+ intel_sdvo_set_output_timing(intel_encoder, &input_dtd);12341229 }1235123012361231 /* Set the input timing to the screen. Assume always input 0. */12371237- intel_sdvo_set_target_input(output, true, false);12321232+ intel_sdvo_set_target_input(intel_encoder, true, false);1238123312391234 if (sdvo_priv->is_tv)12401240- intel_sdvo_set_tv_format(output);12351235+ intel_sdvo_set_tv_format(intel_encoder);1241123612421237 /* We would like to use intel_sdvo_create_preferred_input_timing() to12431238 * provide the device with a timing it can support, if it supports that···12451240 * output the preferred timing, and we don't support that currently.12461241 */12471242#if 012481248- success = intel_sdvo_create_preferred_input_timing(output, clock,12431243+ success = intel_sdvo_create_preferred_input_timing(encoder, clock,12491244 width, height);12501245 if (success) {12511246 struct intel_sdvo_dtd *input_dtd;1252124712531253- intel_sdvo_get_preferred_input_timing(output, &input_dtd);12541254- intel_sdvo_set_input_timing(output, &input_dtd);12481248+ intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);12491249+ intel_sdvo_set_input_timing(encoder, &input_dtd);12551250 }12561251#else12571257- intel_sdvo_set_input_timing(output, &input_dtd);12521252+ intel_sdvo_set_input_timing(intel_encoder, &input_dtd);12581253#endif1259125412601255 switch (intel_sdvo_get_pixel_multiplier(mode)) {12611256 case 1:12621262- intel_sdvo_set_clock_rate_mult(output,12571257+ intel_sdvo_set_clock_rate_mult(intel_encoder,12631258 SDVO_CLOCK_RATE_MULT_1X);12641259 break;12651260 case 2:12661266- intel_sdvo_set_clock_rate_mult(output,12611261+ intel_sdvo_set_clock_rate_mult(intel_encoder,12671262 SDVO_CLOCK_RATE_MULT_2X);12681263 break;12691264 case 4:12701270- intel_sdvo_set_clock_rate_mult(output,12651265+ intel_sdvo_set_clock_rate_mult(intel_encoder,12711266 SDVO_CLOCK_RATE_MULT_4X);12721267 break;12731268 }···12781273 SDVO_VSYNC_ACTIVE_HIGH |12791274 SDVO_HSYNC_ACTIVE_HIGH;12801275 } else {12811281- sdvox |= I915_READ(sdvo_priv->output_device);12821282- switch (sdvo_priv->output_device) {12761276+ sdvox |= I915_READ(sdvo_priv->sdvo_reg);12771277+ switch (sdvo_priv->sdvo_reg) {12831278 case SDVOB:12841279 sdvox &= SDVOB_PRESERVE_MASK;12851280 break;···1303129813041299 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)13051300 sdvox |= SDVO_STALL_SELECT;13061306- intel_sdvo_write_sdvox(output, sdvox);13011301+ intel_sdvo_write_sdvox(intel_encoder, sdvox);13071302}1308130313091304static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)···13201315 intel_sdvo_set_encoder_power_state(intel_encoder, mode);1321131613221317 if (mode == DRM_MODE_DPMS_OFF) {13231323- temp = I915_READ(sdvo_priv->output_device);13181318+ temp = I915_READ(sdvo_priv->sdvo_reg);13241319 if ((temp & SDVO_ENABLE) != 0) {13251320 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);13261321 }···13301325 int i;13311326 u8 status;1332132713331333- temp = I915_READ(sdvo_priv->output_device);13281328+ temp = I915_READ(sdvo_priv->sdvo_reg);13341329 if ((temp & SDVO_ENABLE) == 0)13351330 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);13361331 for (i = 0; i < 2; i++)···13931388 /* XXX: Save TV format/enhancements. */13941389 }1395139013961396- sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);13911391+ sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg);13971392}1398139313991394static void intel_sdvo_restore(struct drm_connector *connector)···1504149915051500 sdvo = iout->dev_priv;1506150115071507- if (sdvo->output_device == SDVOB && sdvoB)15021502+ if (sdvo->sdvo_reg == SDVOB && sdvoB)15081503 return connector;1509150415101510- if (sdvo->output_device == SDVOC && !sdvoB)15051505+ if (sdvo->sdvo_reg == SDVOC && !sdvoB)15111506 return connector;1512150715131508 }···22532248};2254224922552250static u822562256-intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)22512251+intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)22572252{22582253 struct drm_i915_private *dev_priv = dev->dev_private;22592254 struct sdvo_device_mapping *my_mapping, *other_mapping;2260225522612261- if (output_device == SDVOB) {22562256+ if (sdvo_reg == SDVOB) {22622257 my_mapping = &dev_priv->sdvo_mappings[0];22632258 other_mapping = &dev_priv->sdvo_mappings[1];22642259 } else {···22832278 /* No SDVO device info is found for another DVO port,22842279 * so use mapping assumption we had before BIOS parsing.22852280 */22862286- if (output_device == SDVOB)22812281+ if (sdvo_reg == SDVOB)22872282 return 0x70;22882283 else22892284 return 0x72;···27692764 return;27702765}2771276627722772-bool intel_sdvo_init(struct drm_device *dev, int output_device)27672767+bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)27732768{27742769 struct drm_i915_private *dev_priv = dev->dev_private;27752770 struct drm_connector *connector;···27852780 }2786278127872782 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);27882788- sdvo_priv->output_device = output_device;27832783+ sdvo_priv->sdvo_reg = sdvo_reg;2789278427902785 intel_encoder->dev_priv = sdvo_priv;27912786 intel_encoder->type = INTEL_OUTPUT_SDVO;2792278727932788 /* setup the DDC bus. */27942794- if (output_device == SDVOB)27892789+ if (sdvo_reg == SDVOB)27952790 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");27962791 else27972792 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");···27992794 if (!intel_encoder->i2c_bus)28002795 goto err_inteloutput;2801279628022802- sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);27972797+ sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);2803279828042799 /* Save the bit-banging i2c functionality for use by the DDC wrapper */28052800 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;···28082803 for (i = 0; i < 0x40; i++) {28092804 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {28102805 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",28112811- output_device == SDVOB ? 'B' : 'C');28062806+ sdvo_reg == SDVOB ? 'B' : 'C');28122807 goto err_i2c;28132808 }28142809 }2815281028162811 /* setup the DDC bus. */28172817- if (output_device == SDVOB) {28122812+ if (sdvo_reg == SDVOB) {28182813 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");28192814 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,28202815 "SDVOB/VGA DDC BUS");···28382833 if (intel_sdvo_output_setup(intel_encoder,28392834 sdvo_priv->caps.output_flags) != true) {28402835 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",28412841- output_device == SDVOB ? 'B' : 'C');28362836+ sdvo_reg == SDVOB ? 'B' : 'C');28422837 goto err_i2c;28432838 }28442839