tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: mediatek: xsphy: remove macros used to prepare bitfield value

Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local ones anymore.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20220920090038.15133-4-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chunfeng Yun and committed by
Vinod Koul c221baa3 6b5ef194

+17 -29
+17 -29
drivers/phy/mediatek/phy-mtk-xsphy.c
··· 37 37 #define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00) 38 38 #define P2F_RG_FREQDET_EN BIT(24) 39 39 #define P2F_RG_CYCLECNT GENMASK(23, 0) 40 - #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 41 40 42 41 #define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c) 43 42 ··· 49 50 50 51 #define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04) 51 52 #define P2A1_RG_INTR_CAL GENMASK(23, 19) 52 - #define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19) 53 53 #define P2A1_RG_VRT_SEL GENMASK(14, 12) 54 - #define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) 55 54 #define P2A1_RG_TERM_SEL GENMASK(10, 8) 56 - #define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) 57 55 58 56 #define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014) 59 57 #define P2A5_RG_HSTX_SRCAL_EN BIT(15) 60 58 #define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12) 61 - #define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 62 59 63 60 #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018) 64 61 #define P2A6_RG_BC11_SW_EN BIT(23) ··· 69 74 70 75 #define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00) 71 76 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16) 72 - #define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16) 73 77 74 78 #define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04) 75 79 #define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0) 76 - #define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x)) 77 80 78 81 #define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014) 79 82 #define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0) 80 - #define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x)) 81 83 82 84 #define XSP_REF_CLK 26 /* MHZ */ 83 85 #define XSP_SLEW_RATE_COEF 17 ··· 126 134 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); 127 135 128 136 /* set cycle count as 1024 */ 129 - mtk_phy_update_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, 130 - P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT)); 137 + mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, 138 + XSP_FM_DET_CYCLE_CNT); 131 139 132 140 /* enable frequency meter */ 133 141 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); ··· 158 166 xsphy->src_ref_clk, xsphy->src_coef); 159 167 160 168 /* set HS slew rate */ 161 - mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, 162 - P2A5_RG_HSTX_SRCTRL_VAL(calib_val)); 169 + mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val); 163 170 164 171 /* disable USB ring oscillator */ 165 172 mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); ··· 271 280 void __iomem *pbase = inst->port_base; 272 281 273 282 if (inst->efuse_intr) 274 - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, 275 - P2A1_RG_INTR_CAL_VAL(inst->efuse_intr)); 283 + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, 284 + inst->efuse_intr); 276 285 277 286 if (inst->eye_src) 278 - mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, 279 - P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src)); 287 + mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, 288 + inst->eye_src); 280 289 281 290 if (inst->eye_vrt) 282 - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, 283 - P2A1_RG_VRT_SEL_VAL(inst->eye_vrt)); 291 + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, 292 + inst->eye_vrt); 284 293 285 294 if (inst->eye_term) 286 - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, 287 - P2A1_RG_TERM_SEL_VAL(inst->eye_term)); 295 + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, 296 + inst->eye_term); 288 297 } 289 298 290 299 static void u3_phy_props_set(struct mtk_xsphy *xsphy, ··· 293 302 void __iomem *pbase = inst->port_base; 294 303 295 304 if (inst->efuse_intr) 296 - mtk_phy_update_bits(xsphy->glb_base + SSPXTP_PHYA_GLB_00, 297 - RG_XTP_GLB_BIAS_INTR_CTRL, 298 - RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr)); 305 + mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00, 306 + RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr); 299 307 300 308 if (inst->efuse_tx_imp) 301 - mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_04, 302 - RG_XTP_LN0_TX_IMPSEL, 303 - RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp)); 309 + mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04, 310 + RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp); 304 311 305 312 if (inst->efuse_rx_imp) 306 - mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_14, 307 - RG_XTP_LN0_RX_IMPSEL, 308 - RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp)); 313 + mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14, 314 + RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); 309 315 } 310 316 311 317 static int mtk_phy_init(struct phy *phy)