phy: mediatek: tphy: remove macros to prepare bitfield value

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local ones anymore.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20220920090038.15133-3-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chunfeng Yun and committed by

Vinod Koul 3 years ago 6b5ef194 29c07477

+67 -126

1 changed file

expand all

drivers

phy

mediatek

phy-mtk-tphy.c

+67 -126

drivers/phy/mediatek/phy-mtk-tphy.c

··· 49 49 #define U3P_USBPHYACR0 0x000 50 50 #define PA0_RG_U2PLL_FORCE_ON BIT(15) 51 51 #define PA0_USB20_PLL_PREDIV GENMASK(7, 6) 52 - #define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) 53 52 #define PA0_RG_USB20_INTR_EN BIT(5) 54 53 55 54 #define U3P_USBPHYACR1 0x004 56 55 #define PA1_RG_INTR_CAL GENMASK(23, 19) 57 - #define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19) 58 56 #define PA1_RG_VRT_SEL GENMASK(14, 12) 59 - #define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) 60 57 #define PA1_RG_TERM_SEL GENMASK(10, 8) 61 - #define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) 62 58 63 59 #define U3P_USBPHYACR2 0x008 64 60 #define PA2_RG_U2PLL_BW GENMASK(21, 19) 65 - #define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19) 66 61 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 67 62 68 63 #define U3P_USBPHYACR5 0x014 69 64 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 70 65 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 71 - #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 72 66 #define PA5_RG_U2_HS_100U_U3_EN BIT(11) 73 67 74 68 #define U3P_USBPHYACR6 0x018 75 69 #define PA6_RG_U2_PRE_EMP GENMASK(31, 30) 76 - #define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) 77 70 #define PA6_RG_U2_BC11_SW_EN BIT(23) 78 71 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 79 72 #define PA6_RG_U2_DISCTH GENMASK(7, 4) 80 - #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) 81 73 #define PA6_RG_U2_SQTH GENMASK(3, 0) 82 - #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) 83 74 84 75 #define U3P_U2PHYACR4 0x020 85 76 #define P2C_RG_USB20_GPIO_CTL BIT(9) ··· 97 106 #define P2C_FORCE_SUSPENDM BIT(18) 98 107 #define P2C_FORCE_TERMSEL BIT(17) 99 108 #define P2C_RG_DATAIN GENMASK(13, 10) 100 - #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 101 109 #define P2C_RG_DMPULLDOWN BIT(7) 102 110 #define P2C_RG_DPPULLDOWN BIT(6) 103 111 #define P2C_RG_XCVRSEL GENMASK(5, 4) 104 - #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 105 112 #define P2C_RG_SUSPENDM BIT(3) 106 113 #define P2C_RG_TERMSEL BIT(2) 107 114 #define P2C_DTM0_PART_MASK \ ··· 130 141 131 142 #define U3P_U3_PHYA_REG0 0x000 132 143 #define P3A_RG_IEXT_INTR GENMASK(15, 10) 133 - #define P3A_RG_IEXT_INTR_VAL(x) ((0x3f & (x)) << 10) 134 144 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 135 - #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) 136 145 137 146 #define U3P_U3_PHYA_REG1 0x004 138 147 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 139 - #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) 140 148 141 149 #define U3P_U3_PHYA_REG6 0x018 142 150 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 143 - #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 144 151 145 152 #define U3P_U3_PHYA_REG9 0x024 146 153 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 147 - #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 148 154 149 155 #define U3P_U3_PHYA_DA_REG0 0x100 150 156 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 151 - #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) 152 157 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 153 - #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) 154 158 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 155 - #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 156 159 157 160 #define U3P_U3_PHYA_DA_REG4 0x108 158 161 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 159 162 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 160 - #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) 161 163 162 164 #define U3P_U3_PHYA_DA_REG5 0x10c 163 165 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 164 - #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) 165 166 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 166 - #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) 167 167 168 168 #define U3P_U3_PHYA_DA_REG6 0x110 169 169 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 170 - #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) 171 170 172 171 #define U3P_U3_PHYA_DA_REG7 0x114 173 172 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 174 - #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) 175 173 176 174 #define U3P_U3_PHYA_DA_REG20 0x13c 177 175 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 178 - #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) 179 176 180 177 #define U3P_U3_PHYA_DA_REG25 0x148 181 178 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 182 - #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) 183 179 184 180 #define U3P_U3_PHYD_LFPS1 0x00c 185 181 #define P3D_RG_FWAKE_TH GENMASK(21, 16) 186 - #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) 187 182 188 183 #define U3P_U3_PHYD_IMPCAL0 0x010 189 184 #define P3D_RG_FORCE_TX_IMPEL BIT(31) 190 185 #define P3D_RG_TX_IMPEL GENMASK(28, 24) 191 - #define P3D_RG_TX_IMPEL_VAL(x) ((0x1f & (x)) << 24) 192 186 193 187 #define U3P_U3_PHYD_IMPCAL1 0x014 194 188 #define P3D_RG_FORCE_RX_IMPEL BIT(31) 195 189 #define P3D_RG_RX_IMPEL GENMASK(28, 24) 196 - #define P3D_RG_RX_IMPEL_VAL(x) ((0x1f & (x)) << 24) 197 190 198 191 #define U3P_U3_PHYD_RSV 0x054 199 192 #define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12) 200 193 201 194 #define U3P_U3_PHYD_CDR1 0x05c 202 195 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 203 - #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 204 196 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 205 - #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 206 197 207 198 #define U3P_U3_PHYD_RXDET1 0x128 208 199 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 209 - #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) 210 200 211 201 #define U3P_U3_PHYD_RXDET2 0x12c 212 202 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 213 - #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) 214 203 215 204 #define U3P_SPLLC_XTALCTL3 0x018 216 205 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) ··· 196 229 197 230 #define U3P_U2FREQ_FMCR0 0x00 198 231 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) 199 - #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) 200 232 #define P2F_RG_FREQDET_EN BIT(24) 201 233 #define P2F_RG_CYCLECNT GENMASK(23, 0) 202 - #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 203 234 204 235 #define U3P_U2FREQ_VALUE 0x0c 205 236 ··· 214 249 #define PHYD_CTRL_SIGNAL_MODE4 0x1c 215 250 /* CDR Charge Pump P-path current adjustment */ 216 251 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 217 - #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) 218 252 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 219 - #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) 220 253 221 254 #define PHYD_DESIGN_OPTION2 0x24 222 255 /* Symbol lock count selection */ 223 256 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 224 - #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) 225 257 226 258 #define PHYD_DESIGN_OPTION9 0x40 227 259 /* COMWAK GAP width window */ 228 260 #define RG_TG_MAX_MSK GENMASK(20, 16) 229 - #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) 230 261 /* COMINIT GAP width window */ 231 262 #define RG_T2_MAX_MSK GENMASK(13, 8) 232 - #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) 233 263 /* COMWAK GAP width window */ 234 264 #define RG_TG_MIN_MSK GENMASK(7, 5) 235 - #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) 236 265 /* COMINIT GAP width window */ 237 266 #define RG_T2_MIN_MSK GENMASK(4, 0) 238 - #define RG_T2_MIN_VAL(x) (0x1f & (x)) 239 267 240 268 #define ANA_RG_CTRL_SIGNAL1 0x4c 241 269 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 242 270 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 243 - #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) 244 271 245 272 #define ANA_RG_CTRL_SIGNAL4 0x58 246 273 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 247 - #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) 248 274 /* Loop filter R1 resistance adjustment for Gen1 speed */ 249 275 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 250 - #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) 251 276 252 277 #define ANA_RG_CTRL_SIGNAL6 0x60 253 278 /* I-path capacitance adjustment for Gen1 */ 254 279 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 255 - #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) 256 280 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 257 - #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) 258 281 259 282 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 260 283 /* RX Gen1 LEQ tuning step */ 261 284 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 262 - #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) 263 285 264 286 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 265 287 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 266 - #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) 267 288 268 289 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 269 290 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 270 - #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) 271 291 272 292 /* PHY switch between pcie/usb3/sgmii/sata */ 273 293 #define USB_PHY_SWITCH_CTRL 0x0 ··· 364 414 /* set cycle count as 1024, and select u2 channel */ 365 415 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 366 416 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 367 - tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); 417 + tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT); 368 418 if (tphy->pdata->version == MTK_PHY_V1) 369 - tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); 419 + tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1); 370 420 371 421 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 372 422 ··· 399 449 tphy->src_ref_clk, tphy->src_coef); 400 450 401 451 /* set HS slew rate */ 402 - mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 403 - PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val)); 452 + mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 453 + calibration_val); 404 454 405 455 /* disable USB ring oscillator */ 406 456 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); ··· 410 460 struct mtk_phy_instance *instance) 411 461 { 412 462 struct u3phy_banks *u3_banks = &instance->u3_banks; 463 + void __iomem *phya = u3_banks->phya; 464 + void __iomem *phyd = u3_banks->phyd; 413 465 414 466 /* gating PCIe Analog XTAL clock */ 415 467 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, 416 468 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); 417 469 418 470 /* gating XSQ */ 419 - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_DA_REG0, 420 - P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); 471 + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2); 421 472 422 - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG9, 423 - P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); 473 + mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4); 424 474 425 - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG6, 426 - P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); 475 + mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe); 427 476 428 477 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, 429 478 P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, 430 - P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3)); 479 + FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | 480 + FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); 431 481 432 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_LFPS1, 433 - P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34)); 482 + mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34); 434 483 435 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1, 436 - P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); 484 + mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10); 437 485 438 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2, 439 - P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); 486 + mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10); 440 487 441 488 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 442 489 } ··· 447 500 if (!tphy->pdata->sw_pll_48m_to_26m) 448 501 return; 449 502 450 - mtk_phy_update_bits(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 451 - PA0_USB20_PLL_PREDIV_VAL(0)); 503 + mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); 452 504 453 - mtk_phy_update_bits(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 454 - PA2_RG_U2PLL_BW_VAL(3)); 505 + mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); 455 506 456 507 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); 457 508 ··· 495 550 /* DP/DM BC1.1 path Disable */ 496 551 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); 497 552 498 - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); 553 + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); 499 554 500 555 /* Workaround only for mt8195, HW fix it for others (V3) */ 501 556 u2_phy_pll_26m_set(tphy, instance); ··· 598 653 599 654 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, 600 655 P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, 601 - P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); 656 + FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | 657 + FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); 602 658 603 659 /* ref clk drive */ 604 - mtk_phy_update_bits(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 605 - P3A_RG_CLKDRV_AMP_VAL(0x4)); 660 + mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4); 606 661 607 - mtk_phy_update_bits(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 608 - P3A_RG_CLKDRV_OFF_VAL(0x1)); 662 + mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1); 609 663 610 664 /* SSC delta -5000ppm */ 611 - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 612 - P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); 665 + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c); 613 666 614 - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 615 - P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); 667 + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36); 616 668 617 669 /* change pll BW 0.6M */ 618 670 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, 619 671 P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, 620 - P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1)); 672 + FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | 673 + FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); 621 674 622 675 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, 623 676 P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, 624 - P3A_RG_PLL_BC_PE2H_VAL(0x3)); 677 + FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); 625 678 626 - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 627 - P3A_RG_PLL_IR_PE2H_VAL(0x2)); 679 + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2); 628 680 629 - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 630 - P3A_RG_PLL_BP_PE2H_VAL(0xa)); 681 + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa); 631 682 632 683 /* Tx Detect Rx Timing: 10us -> 5us */ 633 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1, 634 - P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); 684 + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, 685 + P3D_RG_RXDET_STB2_SET, 0x10); 635 686 636 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2, 637 - P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); 687 + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, 688 + P3D_RG_RXDET_STB2_SET_P3, 0x10); 638 689 639 690 /* wait for PCIe subsys register to active */ 640 691 usleep_range(2500, 3000); ··· 671 730 /* charge current adjustment */ 672 731 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, 673 732 RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, 674 - RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a)); 733 + FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | 734 + FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); 675 735 676 - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 677 - RG_CDR_BIRLTD0_GEN1_VAL(0x18)); 736 + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18); 678 737 679 - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 680 - RG_CDR_BIRLTD0_GEN3_VAL(0x06)); 738 + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06); 681 739 682 740 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, 683 741 RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, 684 - RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07)); 742 + FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | 743 + FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); 685 744 686 745 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, 687 746 RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, 688 - RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02)); 747 + FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | 748 + FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); 689 749 690 - mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 691 - RG_LOCK_CNT_SEL_VAL(0x02)); 750 + mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02); 692 751 693 752 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 694 753 RG_T2_MIN_MSK | RG_TG_MIN_MSK, 695 - RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04)); 754 + FIELD_PREP(RG_T2_MIN_MSK, 0x12) | 755 + FIELD_PREP(RG_TG_MIN_MSK, 0x04)); 696 756 697 757 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 698 758 RG_T2_MAX_MSK | RG_TG_MAX_MSK, 699 - RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e)); 759 + FIELD_PREP(RG_T2_MAX_MSK, 0x31) | 760 + FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); 700 761 701 - mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 702 - RG_IDRV_0DB_GEN1_VAL(0x20)); 762 + mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20); 703 763 704 - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 705 - RG_EQ_DLEQ_LFI_GEN1_VAL(0x03)); 764 + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03); 706 765 707 766 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 708 767 } ··· 798 857 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); 799 858 800 859 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) 801 - mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 802 - PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src)); 860 + mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 861 + instance->eye_src); 803 862 804 863 if (instance->eye_vrt) 805 - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, 806 - PA1_RG_VRT_SEL_VAL(instance->eye_vrt)); 864 + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, 865 + instance->eye_vrt); 807 866 808 867 if (instance->eye_term) 809 - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, 810 - PA1_RG_TERM_SEL_VAL(instance->eye_term)); 868 + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, 869 + instance->eye_term); 811 870 812 871 if (instance->intr) { 813 872 if (u2_banks->misc) 814 873 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, 815 874 MR1_EFUSE_AUTO_LOAD_DIS); 816 875 817 - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 818 - PA1_RG_INTR_CAL_VAL(instance->intr)); 876 + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 877 + instance->intr); 819 878 } 820 879 821 880 if (instance->discth) 822 - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, 823 - PA6_RG_U2_DISCTH_VAL(instance->discth)); 881 + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, 882 + instance->discth); 824 883 825 884 if (instance->pre_emphasis) 826 - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, 827 - PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis)); 885 + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, 886 + instance->pre_emphasis); 828 887 } 829 888 830 889 /* type switch for usb3/pcie/sgmii/sata */ ··· 973 1032 case PHY_TYPE_USB2: 974 1033 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); 975 1034 976 - mtk_phy_update_bits(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 977 - PA1_RG_INTR_CAL_VAL(instance->efuse_intr)); 1035 + mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 1036 + instance->efuse_intr); 978 1037 break; 979 1038 case PHY_TYPE_USB3: 980 1039 case PHY_TYPE_PCIE: 981 1040 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); 982 1041 983 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, 984 - P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp)); 1042 + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, 1043 + instance->efuse_tx_imp); 985 1044 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); 986 1045 987 - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, 988 - P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp)); 1046 + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, 1047 + instance->efuse_rx_imp); 989 1048 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); 990 1049 991 - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, 992 - P3A_RG_IEXT_INTR_VAL(instance->efuse_intr)); 1050 + mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, 1051 + instance->efuse_intr); 993 1052 break; 994 1053 default: 995 1054 dev_warn(dev, "no sw efuse for type %d\n", instance->type);