tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: at91: make watchdog drivers soc independent
switch the watchdog drivers to resource and pass it via platform_device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+88
-18
+10
-1
arch/arm/mach-at91/at91cap9_devices.c
+10
-1
arch/arm/mach-at91/at91cap9_devices.c
···
694
694
* -------------------------------------------------------------------- */
695
695
696
696
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
697
+
static struct resource wdt_resources[] = {
698
+
{
699
+
.start = AT91CAP9_BASE_WDT,
700
+
.end = AT91CAP9_BASE_WDT + SZ_16 - 1,
701
+
.flags = IORESOURCE_MEM,
702
+
}
703
+
};
704
+
697
705
static struct platform_device at91cap9_wdt_device = {
698
706
.name = "at91_wdt",
699
707
.id = -1,
700
-
.num_resources = 0,
708
+
.resource = wdt_resources,
709
+
.num_resources = ARRAY_SIZE(wdt_resources),
701
710
};
702
711
703
712
static void __init at91_add_device_watchdog(void)
+10
-1
arch/arm/mach-at91/at91sam9260_devices.c
+10
-1
arch/arm/mach-at91/at91sam9260_devices.c
···
738
738
* -------------------------------------------------------------------- */
739
739
740
740
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
741
+
static struct resource wdt_resources[] = {
742
+
{
743
+
.start = AT91SAM9260_BASE_WDT,
744
+
.end = AT91SAM9260_BASE_WDT + SZ_16 - 1,
745
+
.flags = IORESOURCE_MEM,
746
+
}
747
+
};
748
+
741
749
static struct platform_device at91sam9260_wdt_device = {
742
750
.name = "at91_wdt",
743
751
.id = -1,
744
-
.num_resources = 0,
752
+
.resource = wdt_resources,
753
+
.num_resources = ARRAY_SIZE(wdt_resources),
745
754
};
746
755
747
756
static void __init at91_add_device_watchdog(void)
+10
-1
arch/arm/mach-at91/at91sam9261_devices.c
+10
-1
arch/arm/mach-at91/at91sam9261_devices.c
···
624
624
* -------------------------------------------------------------------- */
625
625
626
626
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
627
+
static struct resource wdt_resources[] = {
628
+
{
629
+
.start = AT91SAM9261_BASE_WDT,
630
+
.end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
631
+
.flags = IORESOURCE_MEM,
632
+
}
633
+
};
634
+
627
635
static struct platform_device at91sam9261_wdt_device = {
628
636
.name = "at91_wdt",
629
637
.id = -1,
630
-
.num_resources = 0,
638
+
.resource = wdt_resources,
639
+
.num_resources = ARRAY_SIZE(wdt_resources),
631
640
};
632
641
633
642
static void __init at91_add_device_watchdog(void)
+10
-1
arch/arm/mach-at91/at91sam9263_devices.c
+10
-1
arch/arm/mach-at91/at91sam9263_devices.c
···
996
996
* -------------------------------------------------------------------- */
997
997
998
998
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
999
+
static struct resource wdt_resources[] = {
1000
+
{
1001
+
.start = AT91SAM9263_BASE_WDT,
1002
+
.end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1003
+
.flags = IORESOURCE_MEM,
1004
+
}
1005
+
};
1006
+
999
1007
static struct platform_device at91sam9263_wdt_device = {
1000
1008
.name = "at91_wdt",
1001
1009
.id = -1,
1002
-
.num_resources = 0,
1010
+
.resource = wdt_resources,
1011
+
.num_resources = ARRAY_SIZE(wdt_resources),
1003
1012
};
1004
1013
1005
1014
static void __init at91_add_device_watchdog(void)
+10
-1
arch/arm/mach-at91/at91sam9g45_devices.c
+10
-1
arch/arm/mach-at91/at91sam9g45_devices.c
···
1133
1133
* -------------------------------------------------------------------- */
1134
1134
1135
1135
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1136
+
static struct resource wdt_resources[] = {
1137
+
{
1138
+
.start = AT91SAM9G45_BASE_WDT,
1139
+
.end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1140
+
.flags = IORESOURCE_MEM,
1141
+
}
1142
+
};
1143
+
1136
1144
static struct platform_device at91sam9g45_wdt_device = {
1137
1145
.name = "at91_wdt",
1138
1146
.id = -1,
1139
-
.num_resources = 0,
1147
+
.resource = wdt_resources,
1148
+
.num_resources = ARRAY_SIZE(wdt_resources),
1140
1149
};
1141
1150
1142
1151
static void __init at91_add_device_watchdog(void)
+10
-1
arch/arm/mach-at91/at91sam9rl_devices.c
+10
-1
arch/arm/mach-at91/at91sam9rl_devices.c
···
709
709
* -------------------------------------------------------------------- */
710
710
711
711
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
712
+
static struct resource wdt_resources[] = {
713
+
{
714
+
.start = AT91SAM9RL_BASE_WDT,
715
+
.end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
716
+
.flags = IORESOURCE_MEM,
717
+
}
718
+
};
719
+
712
720
static struct platform_device at91sam9rl_wdt_device = {
713
721
.name = "at91_wdt",
714
722
.id = -1,
715
-
.num_resources = 0,
723
+
.resource = wdt_resources,
724
+
.num_resources = ARRAY_SIZE(wdt_resources),
716
725
};
717
726
718
727
static void __init at91_add_device_watchdog(void)
+1
-1
arch/arm/mach-at91/include/mach/at91cap9.h
+1
-1
arch/arm/mach-at91/include/mach/at91cap9.h
···
86
86
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
87
87
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
88
88
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
89
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
90
89
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
91
90
(0xfffffd50 - AT91_BASE_SYS) : \
92
91
(0xfffffd60 - AT91_BASE_SYS))
···
100
101
#define AT91CAP9_BASE_SHDWC 0xfffffd10
101
102
#define AT91CAP9_BASE_RTT 0xfffffd20
102
103
#define AT91CAP9_BASE_PIT 0xfffffd30
104
+
#define AT91CAP9_BASE_WDT 0xfffffd40
103
105
104
106
#define AT91_USART0 AT91CAP9_BASE_US0
105
107
#define AT91_USART1 AT91CAP9_BASE_US1
+1
-1
arch/arm/mach-at91/include/mach/at91sam9260.h
+1
-1
arch/arm/mach-at91/include/mach/at91sam9260.h
···
86
86
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
87
87
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
88
88
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
89
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
90
89
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
91
90
92
91
#define AT91SAM9260_BASE_ECC 0xffffe800
···
96
97
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
97
98
#define AT91SAM9260_BASE_RTT 0xfffffd20
98
99
#define AT91SAM9260_BASE_PIT 0xfffffd30
100
+
#define AT91SAM9260_BASE_WDT 0xfffffd40
99
101
100
102
#define AT91_USART0 AT91SAM9260_BASE_US0
101
103
#define AT91_USART1 AT91SAM9260_BASE_US1
+1
-1
arch/arm/mach-at91/include/mach/at91sam9261.h
+1
-1
arch/arm/mach-at91/include/mach/at91sam9261.h
···
71
71
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
72
72
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
73
73
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
74
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
75
74
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
76
75
77
76
#define AT91SAM9261_BASE_SMC 0xffffec00
···
80
81
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
81
82
#define AT91SAM9261_BASE_RTT 0xfffffd20
82
83
#define AT91SAM9261_BASE_PIT 0xfffffd30
84
+
#define AT91SAM9261_BASE_WDT 0xfffffd40
83
85
84
86
#define AT91_USART0 AT91SAM9261_BASE_US0
85
87
#define AT91_USART1 AT91SAM9261_BASE_US1
+1
-1
arch/arm/mach-at91/include/mach/at91sam9263.h
+1
-1
arch/arm/mach-at91/include/mach/at91sam9263.h
···
81
81
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
82
82
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
83
83
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
84
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85
84
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
86
85
87
86
#define AT91SAM9263_BASE_ECC0 0xffffe000
···
95
96
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
96
97
#define AT91SAM9263_BASE_RTT0 0xfffffd20
97
98
#define AT91SAM9263_BASE_PIT 0xfffffd30
99
+
#define AT91SAM9263_BASE_WDT 0xfffffd40
98
100
#define AT91SAM9263_BASE_RTT1 0xfffffd50
99
101
100
102
#define AT91_USART0 AT91SAM9263_BASE_US0
+1
-1
arch/arm/mach-at91/include/mach/at91sam9g45.h
+1
-1
arch/arm/mach-at91/include/mach/at91sam9g45.h
···
93
93
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
94
94
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
95
95
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
96
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
97
96
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
98
97
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
99
98
···
107
108
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
108
109
#define AT91SAM9G45_BASE_RTT 0xfffffd20
109
110
#define AT91SAM9G45_BASE_PIT 0xfffffd30
111
+
#define AT91SAM9G45_BASE_WDT 0xfffffd40
110
112
111
113
#define AT91_USART0 AT91SAM9G45_BASE_US0
112
114
#define AT91_USART1 AT91SAM9G45_BASE_US1
+1
-1
arch/arm/mach-at91/include/mach/at91sam9rl.h
+1
-1
arch/arm/mach-at91/include/mach/at91sam9rl.h
···
75
75
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
76
76
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
77
77
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
78
-
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
79
78
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
80
79
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
81
80
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
···
89
90
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
90
91
#define AT91SAM9RL_BASE_RTT 0xfffffd20
91
92
#define AT91SAM9RL_BASE_PIT 0xfffffd30
93
+
#define AT91SAM9RL_BASE_WDT 0xfffffd40
92
94
93
95
#define AT91_USART0 AT91SAM9RL_BASE_US0
94
96
#define AT91_USART1 AT91SAM9RL_BASE_US1
+19
-3
drivers/watchdog/at91sam9_wdt.c
+19
-3
drivers/watchdog/at91sam9_wdt.c
···
35
35
36
36
#define DRV_NAME "AT91SAM9 Watchdog"
37
37
38
+
#define wdt_read(field) \
39
+
__raw_readl(at91wdt_private.base + field)
40
+
#define wdt_write(field, val) \
41
+
__raw_writel((val), at91wdt_private.base + field)
42
+
38
43
/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
39
44
* use this to convert a watchdog
40
45
* value from/to milliseconds.
···
68
63
static void at91_ping(unsigned long data);
69
64
70
65
static struct {
66
+
void __iomem *base;
71
67
unsigned long next_heartbeat; /* the next_heartbeat for the timer */
72
68
unsigned long open;
73
69
char expect_close;
···
83
77
*/
84
78
static inline void at91_wdt_reset(void)
85
79
{
86
-
at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
80
+
wdt_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
87
81
}
88
82
89
83
/*
···
138
132
unsigned int mr;
139
133
140
134
/* Check if disabled */
141
-
mr = at91_sys_read(AT91_WDT_MR);
135
+
mr = wdt_read(AT91_WDT_MR);
142
136
if (mr & AT91_WDT_WDDIS) {
143
137
printk(KERN_ERR DRV_NAME": sorry, watchdog is disabled\n");
144
138
return -EIO;
···
155
149
| AT91_WDT_WDDBGHLT /* disabled in debug mode */
156
150
| AT91_WDT_WDD /* restart at any time */
157
151
| (timeout & AT91_WDT_WDV); /* timer value */
158
-
at91_sys_write(AT91_WDT_MR, reg);
152
+
wdt_write(AT91_WDT_MR, reg);
159
153
160
154
return 0;
161
155
}
···
254
248
255
249
static int __init at91wdt_probe(struct platform_device *pdev)
256
250
{
251
+
struct resource *r;
257
252
int res;
258
253
259
254
if (at91wdt_miscdev.parent)
260
255
return -EBUSY;
261
256
at91wdt_miscdev.parent = &pdev->dev;
257
+
258
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259
+
if (!r)
260
+
return -ENODEV;
261
+
at91wdt_private.base = ioremap(r->start, resource_size(r));
262
+
if (!at91wdt_private.base) {
263
+
dev_err(&pdev->dev, "failed to map registers, aborting.\n");
264
+
return -ENOMEM;
265
+
}
262
266
263
267
/* Set watchdog */
264
268
res = at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
+3
-3
drivers/watchdog/at91sam9_wdt.h
+3
-3
drivers/watchdog/at91sam9_wdt.h
···
16
16
#ifndef AT91_WDT_H
17
17
#define AT91_WDT_H
18
18
19
-
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
19
+
#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
20
20
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
21
21
#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
22
22
23
-
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
23
+
#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
24
24
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
25
25
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
26
26
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
···
30
30
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
31
31
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
32
32
33
-
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
33
+
#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
34
34
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
35
35
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
36
36