tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: at91: make shutdown controler soc independent

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Jean-Christophe PLAGNIOL-VILLARD f22deee5 f466f3bc

+52 -67
+1 -9
arch/arm/mach-at91/at91cap9.c
··· 13 13 */ 14 14 15 15 #include <linux/module.h> 16 - #include <linux/pm.h> 17 16 18 17 #include <asm/irq.h> 19 18 #include <asm/mach/arch.h> ··· 22 23 #include <mach/at91cap9.h> 23 24 #include <mach/at91_pmc.h> 24 25 #include <mach/at91_rstc.h> 25 - #include <mach/at91_shdwc.h> 26 26 27 27 #include "soc.h" 28 28 #include "generic.h" ··· 317 319 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); 318 320 } 319 321 320 - static void at91cap9_poweroff(void) 321 - { 322 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 323 - } 324 - 325 - 326 322 /* -------------------------------------------------------------------- 327 323 * AT91CAP9 processor initialization 328 324 * -------------------------------------------------------------------- */ ··· 328 336 329 337 static void __init at91cap9_ioremap_registers(void) 330 338 { 339 + at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); 331 340 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); 332 341 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); 333 342 } ··· 336 343 static void __init at91cap9_initialize(void) 337 344 { 338 345 at91_arch_reset = at91cap9_reset; 339 - pm_power_off = at91cap9_poweroff; 340 346 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); 341 347 342 348 /* Register GPIO subsystem */
+1 -9
arch/arm/mach-at91/at91sam9260.c
··· 11 11 */ 12 12 13 13 #include <linux/module.h> 14 - #include <linux/pm.h> 15 14 16 15 #include <asm/irq.h> 17 16 #include <asm/mach/arch.h> ··· 20 21 #include <mach/at91sam9260.h> 21 22 #include <mach/at91_pmc.h> 22 23 #include <mach/at91_rstc.h> 23 - #include <mach/at91_shdwc.h> 24 24 25 25 #include "soc.h" 26 26 #include "generic.h" ··· 285 287 } 286 288 }; 287 289 288 - static void at91sam9260_poweroff(void) 289 - { 290 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 291 - } 292 - 293 - 294 290 /* -------------------------------------------------------------------- 295 291 * AT91SAM9260 processor initialization 296 292 * -------------------------------------------------------------------- */ ··· 320 328 321 329 static void __init at91sam9260_ioremap_registers(void) 322 330 { 331 + at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); 323 332 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 324 333 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 325 334 } ··· 328 335 static void __init at91sam9260_initialize(void) 329 336 { 330 337 at91_arch_reset = at91sam9_alt_reset; 331 - pm_power_off = at91sam9260_poweroff; 332 338 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) 333 339 | (1 << AT91SAM9260_ID_IRQ2); 334 340
+1 -9
arch/arm/mach-at91/at91sam9261.c
··· 11 11 */ 12 12 13 13 #include <linux/module.h> 14 - #include <linux/pm.h> 15 14 16 15 #include <asm/irq.h> 17 16 #include <asm/mach/arch.h> ··· 19 20 #include <mach/at91sam9261.h> 20 21 #include <mach/at91_pmc.h> 21 22 #include <mach/at91_rstc.h> 22 - #include <mach/at91_shdwc.h> 23 23 24 24 #include "soc.h" 25 25 #include "generic.h" ··· 266 268 } 267 269 }; 268 270 269 - static void at91sam9261_poweroff(void) 270 - { 271 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 272 - } 273 - 274 - 275 271 /* -------------------------------------------------------------------- 276 272 * AT91SAM9261 processor initialization 277 273 * -------------------------------------------------------------------- */ ··· 280 288 281 289 static void __init at91sam9261_ioremap_registers(void) 282 290 { 291 + at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); 283 292 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 284 293 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 285 294 } ··· 288 295 static void __init at91sam9261_initialize(void) 289 296 { 290 297 at91_arch_reset = at91sam9_alt_reset; 291 - pm_power_off = at91sam9261_poweroff; 292 298 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) 293 299 | (1 << AT91SAM9261_ID_IRQ2); 294 300
+1 -9
arch/arm/mach-at91/at91sam9263.c
··· 11 11 */ 12 12 13 13 #include <linux/module.h> 14 - #include <linux/pm.h> 15 14 16 15 #include <asm/irq.h> 17 16 #include <asm/mach/arch.h> ··· 18 19 #include <mach/at91sam9263.h> 19 20 #include <mach/at91_pmc.h> 20 21 #include <mach/at91_rstc.h> 21 - #include <mach/at91_shdwc.h> 22 22 23 23 #include "soc.h" 24 24 #include "generic.h" ··· 286 288 } 287 289 }; 288 290 289 - static void at91sam9263_poweroff(void) 290 - { 291 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 292 - } 293 - 294 - 295 291 /* -------------------------------------------------------------------- 296 292 * AT91SAM9263 processor initialization 297 293 * -------------------------------------------------------------------- */ ··· 298 306 299 307 static void __init at91sam9263_ioremap_registers(void) 300 308 { 309 + at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); 301 310 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 302 311 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 303 312 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); ··· 307 314 static void __init at91sam9263_initialize(void) 308 315 { 309 316 at91_arch_reset = at91sam9_alt_reset; 310 - pm_power_off = at91sam9263_poweroff; 311 317 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); 312 318 313 319 /* Register GPIO subsystem */
+1 -9
arch/arm/mach-at91/at91sam9g45.c
··· 11 11 */ 12 12 13 13 #include <linux/module.h> 14 - #include <linux/pm.h> 15 14 #include <linux/dma-mapping.h> 16 15 17 16 #include <asm/irq.h> ··· 19 20 #include <mach/at91sam9g45.h> 20 21 #include <mach/at91_pmc.h> 21 22 #include <mach/at91_rstc.h> 22 - #include <mach/at91_shdwc.h> 23 23 #include <mach/cpu.h> 24 24 25 25 #include "soc.h" ··· 321 323 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); 322 324 } 323 325 324 - static void at91sam9g45_poweroff(void) 325 - { 326 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 327 - } 328 - 329 - 330 326 /* -------------------------------------------------------------------- 331 327 * AT91SAM9G45 processor initialization 332 328 * -------------------------------------------------------------------- */ ··· 333 341 334 342 static void __init at91sam9g45_ioremap_registers(void) 335 343 { 344 + at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); 336 345 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 337 346 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 338 347 } ··· 341 348 static void __init at91sam9g45_initialize(void) 342 349 { 343 350 at91_arch_reset = at91sam9g45_reset; 344 - pm_power_off = at91sam9g45_poweroff; 345 351 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); 346 352 347 353 /* Register GPIO subsystem */
+1 -9
arch/arm/mach-at91/at91sam9rl.c
··· 10 10 */ 11 11 12 12 #include <linux/module.h> 13 - #include <linux/pm.h> 14 13 15 14 #include <asm/irq.h> 16 15 #include <asm/mach/arch.h> ··· 19 20 #include <mach/at91sam9rl.h> 20 21 #include <mach/at91_pmc.h> 21 22 #include <mach/at91_rstc.h> 22 - #include <mach/at91_shdwc.h> 23 23 24 24 #include "soc.h" 25 25 #include "generic.h" ··· 262 264 } 263 265 }; 264 266 265 - static void at91sam9rl_poweroff(void) 266 - { 267 - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 268 - } 269 - 270 - 271 267 /* -------------------------------------------------------------------- 272 268 * AT91SAM9RL processor initialization 273 269 * -------------------------------------------------------------------- */ ··· 285 293 286 294 static void __init at91sam9rl_ioremap_registers(void) 287 295 { 296 + at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); 288 297 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 289 298 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 290 299 } ··· 293 300 static void __init at91sam9rl_initialize(void) 294 301 { 295 302 at91_arch_reset = at91sam9_alt_reset; 296 - pm_power_off = at91sam9rl_poweroff; 297 303 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); 298 304 299 305 /* Register GPIO subsystem */
+1 -1
arch/arm/mach-at91/board-qil-a9260.c
··· 251 251 /* LEDs */ 252 252 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 253 253 /* shutdown controller, wakeup button (5 msec low) */ 254 - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW 254 + at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW 255 255 | AT91_SHDW_RTTWKEN); 256 256 } 257 257
+1 -1
arch/arm/mach-at91/board-usb-a926x.c
··· 344 344 /* I2C */ 345 345 at91_add_device_i2c(NULL, 0); 346 346 /* shutdown controller, wakeup button (5 msec low) */ 347 - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) 347 + at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) 348 348 | AT91_SHDW_WKMODE0_LOW 349 349 | AT91_SHDW_RTTWKEN); 350 350 }
+3
arch/arm/mach-at91/generic.h
··· 60 60 /* reset */ 61 61 extern void at91sam9_alt_reset(void); 62 62 63 + /* shutdown */ 64 + extern void at91_ioremap_shdwc(u32 base_addr); 65 + 63 66 /* GPIO */ 64 67 #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ 65 68 #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
+13 -3
arch/arm/mach-at91/include/mach/at91_shdwc.h
··· 16 16 #ifndef AT91_SHDWC_H 17 17 #define AT91_SHDWC_H 18 18 19 - #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ 19 + #ifndef __ASSEMBLY__ 20 + extern void __iomem *at91_shdwc_base; 21 + 22 + #define at91_shdwc_read(field) \ 23 + __raw_readl(at91_shdwc_base + field) 24 + 25 + #define at91_shdwc_write(field, value) \ 26 + __raw_writel(value, at91_shdwc_base + field); 27 + #endif 28 + 29 + #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ 20 30 #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ 21 31 #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ 22 32 23 - #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ 33 + #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ 24 34 #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ 25 35 #define AT91_SHDW_WKMODE0_NONE 0 26 36 #define AT91_SHDW_WKMODE0_HIGH 1 ··· 40 30 #define AT91_SHDW_CPTWK0_(x) ((x) << 4) 41 31 #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ 42 32 43 - #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ 33 + #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */ 44 34 #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ 45 35 #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ 46 36 #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
+1 -1
arch/arm/mach-at91/include/mach/at91cap9.h
··· 86 86 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 87 87 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 88 88 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 89 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 90 89 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 91 90 #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 92 91 (0xfffffd50 - AT91_BASE_SYS) : \ ··· 98 99 #define AT91CAP9_BASE_PIOB 0xfffff400 99 100 #define AT91CAP9_BASE_PIOC 0xfffff600 100 101 #define AT91CAP9_BASE_PIOD 0xfffff800 102 + #define AT91CAP9_BASE_SHDWC 0xfffffd10 101 103 #define AT91CAP9_BASE_RTT 0xfffffd20 102 104 #define AT91CAP9_BASE_PIT 0xfffffd30 103 105
+1 -1
arch/arm/mach-at91/include/mach/at91sam9260.h
··· 86 86 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 87 87 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 88 88 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 89 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 90 89 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 91 90 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 92 91 ··· 94 95 #define AT91SAM9260_BASE_PIOA 0xfffff400 95 96 #define AT91SAM9260_BASE_PIOB 0xfffff600 96 97 #define AT91SAM9260_BASE_PIOC 0xfffff800 98 + #define AT91SAM9260_BASE_SHDWC 0xfffffd10 97 99 #define AT91SAM9260_BASE_RTT 0xfffffd20 98 100 #define AT91SAM9260_BASE_PIT 0xfffffd30 99 101
+1 -1
arch/arm/mach-at91/include/mach/at91sam9261.h
··· 71 71 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 72 72 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 73 73 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 74 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 75 74 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 76 75 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 77 76 ··· 78 79 #define AT91SAM9261_BASE_PIOA 0xfffff400 79 80 #define AT91SAM9261_BASE_PIOB 0xfffff600 80 81 #define AT91SAM9261_BASE_PIOC 0xfffff800 82 + #define AT91SAM9261_BASE_SHDWC 0xfffffd10 81 83 #define AT91SAM9261_BASE_RTT 0xfffffd20 82 84 #define AT91SAM9261_BASE_PIT 0xfffffd30 83 85
+1 -1
arch/arm/mach-at91/include/mach/at91sam9263.h
··· 81 81 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 82 82 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 83 83 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 84 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 85 84 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 86 85 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 87 86 ··· 93 94 #define AT91SAM9263_BASE_PIOC 0xfffff600 94 95 #define AT91SAM9263_BASE_PIOD 0xfffff800 95 96 #define AT91SAM9263_BASE_PIOE 0xfffffa00 97 + #define AT91SAM9263_BASE_SHDWC 0xfffffd10 96 98 #define AT91SAM9263_BASE_RTT0 0xfffffd20 97 99 #define AT91SAM9263_BASE_PIT 0xfffffd30 98 100 #define AT91SAM9263_BASE_RTT1 0xfffffd50
+1 -1
arch/arm/mach-at91/include/mach/at91sam9g45.h
··· 93 93 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 94 94 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 95 95 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 96 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 97 96 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 98 97 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 99 98 #define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) ··· 105 106 #define AT91SAM9G45_BASE_PIOC 0xfffff600 106 107 #define AT91SAM9G45_BASE_PIOD 0xfffff800 107 108 #define AT91SAM9G45_BASE_PIOE 0xfffffa00 109 + #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 108 110 #define AT91SAM9G45_BASE_RTT 0xfffffd20 109 111 #define AT91SAM9G45_BASE_PIT 0xfffffd30 110 112
+1 -1
arch/arm/mach-at91/include/mach/at91sam9rl.h
··· 75 75 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 76 76 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 77 77 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 78 - #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 79 78 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 80 79 #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 81 80 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) ··· 87 88 #define AT91SAM9RL_BASE_PIOB 0xfffff600 88 89 #define AT91SAM9RL_BASE_PIOC 0xfffff800 89 90 #define AT91SAM9RL_BASE_PIOD 0xfffffa00 91 + #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 90 92 #define AT91SAM9RL_BASE_RTT 0xfffffd20 91 93 #define AT91SAM9RL_BASE_PIT 0xfffffd30 92 94
+5 -2
arch/arm/mach-at91/pm.c
··· 34 34 /* 35 35 * Show the reason for the previous system reset. 36 36 */ 37 - #if defined(AT91_SHDWC) 37 + #if defined(AT91_RSTC) 38 38 39 39 #include <mach/at91_rstc.h> 40 40 #include <mach/at91_shdwc.h> ··· 58 58 char *reason, *r2 = reset; 59 59 u32 reset_type, wake_type; 60 60 61 + if (!at91_shdwc_base) 62 + return; 63 + 61 64 reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; 62 - wake_type = at91_sys_read(AT91_SHDW_SR); 65 + wake_type = at91_shdwc_read(AT91_SHDW_SR); 63 66 64 67 switch (reset_type) { 65 68 case AT91_RSTC_RSTTYP_GENERAL:
+17
arch/arm/mach-at91/setup.c
··· 8 8 #include <linux/module.h> 9 9 #include <linux/io.h> 10 10 #include <linux/mm.h> 11 + #include <linux/pm.h> 11 12 12 13 #include <asm/mach/map.h> 13 14 ··· 16 15 #include <mach/cpu.h> 17 16 #include <mach/at91_dbgu.h> 18 17 #include <mach/at91_pmc.h> 18 + #include <mach/at91_shdwc.h> 19 19 20 20 #include "soc.h" 21 21 #include "generic.h" ··· 285 283 286 284 if (at91_boot_soc.map_io) 287 285 at91_boot_soc.map_io(); 286 + } 287 + 288 + void __iomem *at91_shdwc_base = NULL; 289 + 290 + static void at91sam9_poweroff(void) 291 + { 292 + at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 293 + } 294 + 295 + void __init at91_ioremap_shdwc(u32 base_addr) 296 + { 297 + at91_shdwc_base = ioremap(base_addr, 16); 298 + if (!at91_shdwc_base) 299 + panic("Impossible to ioremap at91_shdwc_base\n"); 300 + pm_power_off = at91sam9_poweroff; 288 301 } 289 302 290 303 void __init at91_initialize(unsigned long main_clock)