Merge branch '20251030-gcc_kaanapali-v2-v2-3-a774a587af6f@oss.qualcomm.com' into clk-for-6.19

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge Kaanapali RPMh, TCSR and global clock controllers through a topic
branch, so they can be made available in the DeviceTree branch as well.

Bjorn Andersson 5 months ago c1a7ebaa a4aa1ceb

+249 -2

4 changed files

expand all

Documentation

devicetree

bindings

clock

qcom,rpmhcc.yaml

qcom,sm8550-tcsr.yaml

qcom,sm8750-gcc.yaml

include

dt-bindings

clock

qcom,kaanapali-gcc.h

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

··· 18 18 compatible: 19 19 enum: 20 20 - qcom,glymur-rpmh-clk 21 + - qcom,kaanapali-rpmh-clk 21 22 - qcom,milos-rpmh-clk 22 23 - qcom,qcs615-rpmh-clk 23 24 - qcom,qdu1000-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

··· 25 25 items: 26 26 - enum: 27 27 - qcom,glymur-tcsr 28 + - qcom,kaanapali-tcsr 28 29 - qcom,milos-tcsr 29 30 - qcom,sar2130p-tcsr 30 31 - qcom,sm8550-tcsr

+6 -2

Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml

··· 13 13 Qualcomm global clock control module provides the clocks, resets and power 14 14 domains on SM8750 15 15 16 - See also: include/dt-bindings/clock/qcom,sm8750-gcc.h 16 + See also: 17 + include/dt-bindings/clock/qcom,kaanapali-gcc.h 18 + include/dt-bindings/clock/qcom,sm8750-gcc.h 17 19 18 20 properties: 19 21 compatible: 20 - const: qcom,sm8750-gcc 22 + enum: 23 + - qcom,kaanapali-gcc 24 + - qcom,sm8750-gcc 21 25 22 26 clocks: 23 27 items:

+241

include/dt-bindings/clock/qcom,kaanapali-gcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H 8 + 9 + /* GCC clocks */ 10 + #define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 11 + #define GCC_AGGRE_UFS_PHY_AXI_CLK 1 12 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 2 13 + #define GCC_BOOT_ROM_AHB_CLK 3 14 + #define GCC_CAM_BIST_MCLK_AHB_CLK 4 15 + #define GCC_CAMERA_AHB_CLK 5 16 + #define GCC_CAMERA_HF_AXI_CLK 6 17 + #define GCC_CAMERA_SF_AXI_CLK 7 18 + #define GCC_CAMERA_XO_CLK 8 19 + #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 20 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 21 + #define GCC_CNOC_PCIE_SF_AXI_CLK 11 22 + #define GCC_DDRSS_PCIE_SF_QTB_CLK 12 23 + #define GCC_QMIP_CAMERA_CMD_AHB_CLK 13 24 + #define GCC_DISP_HF_AXI_CLK 14 25 + #define GCC_DISP_SF_AXI_CLK 15 26 + #define GCC_EVA_AHB_CLK 16 27 + #define GCC_EVA_AXI0_CLK 17 28 + #define GCC_EVA_AXI0C_CLK 18 29 + #define GCC_EVA_XO_CLK 19 30 + #define GCC_GP1_CLK 20 31 + #define GCC_GP1_CLK_SRC 21 32 + #define GCC_GP2_CLK 22 33 + #define GCC_GP2_CLK_SRC 23 34 + #define GCC_GP3_CLK 24 35 + #define GCC_GP3_CLK_SRC 25 36 + #define GCC_GPLL0 26 37 + #define GCC_GPLL0_OUT_EVEN 27 38 + #define GCC_GPLL1 28 39 + #define GCC_GPLL4 29 40 + #define GCC_GPLL7 30 41 + #define GCC_GPLL9 31 42 + #define GCC_GPU_CFG_AHB_CLK 32 43 + #define GCC_GPU_GEMNOC_GFX_CLK 33 44 + #define GCC_GPU_GPLL0_CLK_SRC 34 45 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 46 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 36 47 + #define GCC_QMIP_GPU_AHB_CLK 37 48 + #define GCC_PCIE_0_AUX_CLK 38 49 + #define GCC_PCIE_0_AUX_CLK_SRC 39 50 + #define GCC_PCIE_0_CFG_AHB_CLK 40 51 + #define GCC_PCIE_0_MSTR_AXI_CLK 41 52 + #define GCC_PCIE_0_PHY_AUX_CLK 42 53 + #define GCC_PCIE_0_PHY_AUX_CLK_SRC 43 54 + #define GCC_PCIE_0_PHY_RCHNG_CLK 44 55 + #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45 56 + #define GCC_PCIE_0_PIPE_CLK 46 57 + #define GCC_PCIE_0_PIPE_CLK_SRC 47 58 + #define GCC_PCIE_0_SLV_AXI_CLK 48 59 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 60 + #define GCC_PCIE_RSCC_CFG_AHB_CLK 50 61 + #define GCC_PCIE_RSCC_XO_CLK 51 62 + #define GCC_PDM2_CLK 52 63 + #define GCC_PDM2_CLK_SRC 53 64 + #define GCC_PDM_AHB_CLK 54 65 + #define GCC_PDM_XO4_CLK 55 66 + #define GCC_QUPV3_I2C_CORE_CLK 56 67 + #define GCC_QUPV3_I2C_S0_CLK 57 68 + #define GCC_QUPV3_I2C_S0_CLK_SRC 58 69 + #define GCC_QUPV3_I2C_S1_CLK 59 70 + #define GCC_QUPV3_I2C_S1_CLK_SRC 60 71 + #define GCC_QUPV3_I2C_S2_CLK 61 72 + #define GCC_QUPV3_I2C_S2_CLK_SRC 62 73 + #define GCC_QUPV3_I2C_S3_CLK 63 74 + #define GCC_QUPV3_I2C_S3_CLK_SRC 64 75 + #define GCC_QUPV3_I2C_S4_CLK 65 76 + #define GCC_QUPV3_I2C_S4_CLK_SRC 66 77 + #define GCC_QUPV3_I2C_S_AHB_CLK 67 78 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 68 79 + #define GCC_QUPV3_WRAP1_CORE_CLK 69 80 + #define GCC_QUPV3_WRAP1_QSPI_REF_CLK 70 81 + #define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 71 82 + #define GCC_QUPV3_WRAP1_S0_CLK 72 83 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 84 + #define GCC_QUPV3_WRAP1_S1_CLK 74 85 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 86 + #define GCC_QUPV3_WRAP1_S2_CLK 76 87 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 88 + #define GCC_QUPV3_WRAP1_S3_CLK 78 89 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 90 + #define GCC_QUPV3_WRAP1_S4_CLK 80 91 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 92 + #define GCC_QUPV3_WRAP1_S5_CLK 82 93 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 94 + #define GCC_QUPV3_WRAP1_S6_CLK 84 95 + #define GCC_QUPV3_WRAP1_S6_CLK_SRC 85 96 + #define GCC_QUPV3_WRAP1_S7_CLK 86 97 + #define GCC_QUPV3_WRAP1_S7_CLK_SRC 87 98 + #define GCC_QUPV3_WRAP2_CORE_2X_CLK 88 99 + #define GCC_QUPV3_WRAP2_CORE_CLK 89 100 + #define GCC_QUPV3_WRAP2_S0_CLK 90 101 + #define GCC_QUPV3_WRAP2_S0_CLK_SRC 91 102 + #define GCC_QUPV3_WRAP2_S1_CLK 92 103 + #define GCC_QUPV3_WRAP2_S1_CLK_SRC 93 104 + #define GCC_QUPV3_WRAP2_S2_CLK 94 105 + #define GCC_QUPV3_WRAP2_S2_CLK_SRC 95 106 + #define GCC_QUPV3_WRAP2_S3_CLK 96 107 + #define GCC_QUPV3_WRAP2_S3_CLK_SRC 97 108 + #define GCC_QUPV3_WRAP2_S4_CLK 98 109 + #define GCC_QUPV3_WRAP2_S4_CLK_SRC 99 110 + #define GCC_QUPV3_WRAP3_CORE_2X_CLK 100 111 + #define GCC_QUPV3_WRAP3_CORE_CLK 101 112 + #define GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC 102 113 + #define GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK 103 114 + #define GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK 104 115 + #define GCC_QUPV3_WRAP3_S0_CLK 105 116 + #define GCC_QUPV3_WRAP3_S0_CLK_SRC 106 117 + #define GCC_QUPV3_WRAP3_S1_CLK 107 118 + #define GCC_QUPV3_WRAP3_S1_CLK_SRC 108 119 + #define GCC_QUPV3_WRAP3_S2_CLK 109 120 + #define GCC_QUPV3_WRAP3_S2_CLK_SRC 110 121 + #define GCC_QUPV3_WRAP3_S3_CLK 111 122 + #define GCC_QUPV3_WRAP3_S3_CLK_SRC 112 123 + #define GCC_QUPV3_WRAP3_S4_CLK 113 124 + #define GCC_QUPV3_WRAP3_S4_CLK_SRC 114 125 + #define GCC_QUPV3_WRAP3_S5_CLK 115 126 + #define GCC_QUPV3_WRAP3_S5_CLK_SRC 116 127 + #define GCC_QUPV3_WRAP4_CORE_2X_CLK 117 128 + #define GCC_QUPV3_WRAP4_CORE_CLK 118 129 + #define GCC_QUPV3_WRAP4_S0_CLK 119 130 + #define GCC_QUPV3_WRAP4_S0_CLK_SRC 120 131 + #define GCC_QUPV3_WRAP4_S1_CLK 121 132 + #define GCC_QUPV3_WRAP4_S1_CLK_SRC 122 133 + #define GCC_QUPV3_WRAP4_S2_CLK 123 134 + #define GCC_QUPV3_WRAP4_S2_CLK_SRC 124 135 + #define GCC_QUPV3_WRAP4_S3_CLK 125 136 + #define GCC_QUPV3_WRAP4_S3_CLK_SRC 126 137 + #define GCC_QUPV3_WRAP4_S4_CLK 127 138 + #define GCC_QUPV3_WRAP4_S4_CLK_SRC 128 139 + #define GCC_QUPV3_WRAP_1_M_AXI_CLK 129 140 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 130 141 + #define GCC_QUPV3_WRAP_2_M_AHB_CLK 131 142 + #define GCC_QUPV3_WRAP_2_S_AHB_CLK 132 143 + #define GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK 133 144 + #define GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK 134 145 + #define GCC_QUPV3_WRAP_3_M_AHB_CLK 135 146 + #define GCC_QUPV3_WRAP_3_S_AHB_CLK 136 147 + #define GCC_QUPV3_WRAP_4_M_AHB_CLK 137 148 + #define GCC_QUPV3_WRAP_4_S_AHB_CLK 138 149 + #define GCC_SDCC2_AHB_CLK 139 150 + #define GCC_SDCC2_APPS_CLK 140 151 + #define GCC_SDCC2_APPS_CLK_SRC 141 152 + #define GCC_SDCC4_AHB_CLK 142 153 + #define GCC_SDCC4_APPS_CLK 143 154 + #define GCC_SDCC4_APPS_CLK_SRC 144 155 + #define GCC_UFS_PHY_AHB_CLK 145 156 + #define GCC_UFS_PHY_AXI_CLK 146 157 + #define GCC_UFS_PHY_AXI_CLK_SRC 147 158 + #define GCC_UFS_PHY_ICE_CORE_CLK 148 159 + #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149 160 + #define GCC_UFS_PHY_PHY_AUX_CLK 150 161 + #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 151 162 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 152 163 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 153 164 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 154 165 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 155 166 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156 167 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 157 168 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK 158 169 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 159 170 + #define GCC_USB30_PRIM_MASTER_CLK 160 171 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 161 172 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 162 173 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163 174 + #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164 175 + #define GCC_USB30_PRIM_SLEEP_CLK 165 176 + #define GCC_USB3_PRIM_PHY_AUX_CLK 166 177 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 167 178 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 168 179 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 169 180 + #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 170 181 + #define GCC_VIDEO_AHB_CLK 171 182 + #define GCC_VIDEO_AXI0_CLK 172 183 + #define GCC_VIDEO_AXI1_CLK 173 184 + #define GCC_VIDEO_XO_CLK 174 185 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 175 186 + #define GCC_QMIP_CAMERA_RT_AHB_CLK 176 187 + #define GCC_QMIP_DISP_DCP_SF_AHB_CLK 177 188 + #define GCC_QMIP_PCIE_AHB_CLK 178 189 + #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 179 190 + #define GCC_QMIP_VIDEO_CVP_AHB_CLK 180 191 + #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 181 192 + #define GCC_DISP_AHB_CLK 182 193 + 194 + /* GCC power domains */ 195 + #define GCC_PCIE_0_GDSC 0 196 + #define GCC_PCIE_0_PHY_GDSC 1 197 + #define GCC_UFS_MEM_PHY_GDSC 2 198 + #define GCC_UFS_PHY_GDSC 3 199 + #define GCC_USB30_PRIM_GDSC 4 200 + #define GCC_USB3_PHY_GDSC 5 201 + 202 + /* GCC resets */ 203 + #define GCC_CAMERA_BCR 0 204 + #define GCC_DISPLAY_BCR 1 205 + #define GCC_EVA_AXI0_CLK_ARES 2 206 + #define GCC_EVA_AXI0C_CLK_ARES 3 207 + #define GCC_EVA_BCR 4 208 + #define GCC_GPU_BCR 5 209 + #define GCC_PCIE_0_BCR 6 210 + #define GCC_PCIE_0_LINK_DOWN_BCR 7 211 + #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 8 212 + #define GCC_PCIE_0_PHY_BCR 9 213 + #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 10 214 + #define GCC_PCIE_PHY_BCR 11 215 + #define GCC_PCIE_PHY_CFG_AHB_BCR 12 216 + #define GCC_PCIE_PHY_COM_BCR 13 217 + #define GCC_PCIE_RSCC_BCR 14 218 + #define GCC_PDM_BCR 15 219 + #define GCC_QUPV3_WRAPPER_1_BCR 16 220 + #define GCC_QUPV3_WRAPPER_2_BCR 17 221 + #define GCC_QUPV3_WRAPPER_3_BCR 18 222 + #define GCC_QUPV3_WRAPPER_4_BCR 19 223 + #define GCC_QUPV3_WRAPPER_I2C_BCR 20 224 + #define GCC_QUSB2PHY_PRIM_BCR 21 225 + #define GCC_QUSB2PHY_SEC_BCR 22 226 + #define GCC_SDCC2_BCR 23 227 + #define GCC_SDCC4_BCR 24 228 + #define GCC_UFS_PHY_BCR 25 229 + #define GCC_USB30_PRIM_BCR 26 230 + #define GCC_USB3_DP_PHY_PRIM_BCR 27 231 + #define GCC_USB3_DP_PHY_SEC_BCR 28 232 + #define GCC_USB3_PHY_PRIM_BCR 29 233 + #define GCC_USB3_PHY_SEC_BCR 30 234 + #define GCC_USB3PHY_PHY_PRIM_BCR 31 235 + #define GCC_USB3PHY_PHY_SEC_BCR 32 236 + #define GCC_VIDEO_AXI0_CLK_ARES 33 237 + #define GCC_VIDEO_AXI1_CLK_ARES 34 238 + #define GCC_VIDEO_BCR 35 239 + #define GCC_VIDEO_XO_CLK_ARES 36 240 + 241 + #endif